This paper provides insights on three different possibilities, for transferring data gathered by one field-programmable gate array (FPGA) design to a second one. Typical use case are scenarios where some initial calibration needs to be performed, before a special controller algorithm can be applied. For demonstration and evaluation purposes, this paper uses a real world, active noise control (ANC) application as an example scenario. This application requires specific memory elements of various types to be static while as much of the remaining hardware resources as possible shall be changed dynamically between two configurations. The first approach uses a serial communication protocol to extract the data from the first configuration and insert it into the second configuration. The second approach uses the classic dynamic partial reconfiguration (DPR) design flow for Xilinx FPGAs. The third approach, which is a novel approach, uses a technique called context save restore (CSR) that is not officially supported by the vendor. This technique manipulates the second configuration bit file to import the data, previously gathered by and extracted from the first configuration bit file. Not by means of an additional communication interface, but by exploiting the features of an FPGAs configuration interfaces. The advantages and disadvantages in terms of hardware resource overhead, processing demand and feasibility of these three approaches are evaluated and discussed.

The most used algorithm in active noise control (ANC) applications is the filtered-x least mean square (FxLMS). For large scale systems with multiple inputs and outputs the computational demand of the FxLMS is rising rapidly. Conventional solutions, running on digital signal processors (DSPs), have limitations in parallel computing. In this work a parameterizable multiple input-multiple output (MIMO) feedback FxLMS architecture for field-programmable gate array (FPGA) platforms is presented that can easily be optimized for high-performance or resource efficient computation. The implementation is validated in a real-time practical application using an active headrest with 2x2 channels. The noise reduction is evaluated over various configurations with increasing performance and the respective synthesis results are presented. Here the noise reduction does benefit from the additional computational performance gains. An additional configuration with llxll channels and filter lengths of 2049 at a sample rate of 40 kHz is shown as a benchmark on high-end FPGAs.

In this paper a field programmable gate array (FPGA) is considered as a digital signal processing platform for the implementation of an exponential sine sweep measurement algorithm. Aiming at minimizing the required computational resources, two strategies are proposed. Firstly, an oscillator implemented with the coordinate rotation digital computer (CORDIC) algorithm is used to generate the exponential sine sweep. Secondly, only the calculations are performed that lead to the linear impulse response of the system for a desired length. Furthermore, aiming at minimizing the required memory resources, the measured impulse response is stored in the memory previously allocated to the recorded signal. In order to validate the proposed implementation, measurements of an acoustical system are performed using a platform that is equipped with an FPGA and a processor. In this way, the results achieved by the FPGA fixed-point implementation can be compared to reference results achieved using a floating-point MATLAB implementation running on the processor. This comparison corroborates the validity of the proposed implementation.

The security of embedded devices is very important today because critical infrastructures like medical devices, transportation, communication, and smart grids deploy them in large numbers. In all of these areas cybersecurity is the enabler for safety as failing or compromised devices threaten the life of people. Often, it is not feasible securing already deployed devices because of high costs, missing physical access, or defective hardware. Therefore, the next generation devices deployed in the future have to be more secure and more resilient to cyber attacks.This paper proposes a new approach to secure these next generation devices by using program optimized Application Specific Processors (ASPs) and employing an easy to integrate development flow for embedded developers. It evaluates the security improvement by analyzing the vulnerability of the approach against typical attack patterns.

A timer and interrupt management infrastructure is essential for a computer system executing a preemptive operating system. This holds for single- and also for multicore systems. When it comes to OS-capable ISA-heterogeneous multicore systems (systems that include cores of different ISAs, which all are capable of executing an operating system) the different timer and interrupt infrastructures of the different system ISAs are still applicable. However, if reconfigurability is added on top of the ISA heterogeneity, meaning that the composition (number of individual cores) is runtime adaptable, the timer and interrupt management infrastructure needs to be reconsidered. In this paper, a unified timer and interrupt management scheme is deduced for a runtime adaptable, OS-capable, ISA-heterogeneous multi-core system, consisting of ARM and RISC-V cores, that are capable of executing Linux. This is done by analyzing/surveying the timer and interrupt management schemes of RISC-V and ARM systems. Finally this paper will show that RISC-V timer and interrupt management devices are suitable to also manage timers and interrupts for ARM based systems.

In the past the security of building automation solely depended on the security of the devices inside or tightly connected to the building. In the last years more devices evolved using some kind of cloud service as a back-end or providers supplying some kind of device to the user. Also, the number of building automation systems connected to the Internet for management, control, and data storage increases every year. These developments cause the appearance of new threats on building automation. As Internet of Thing (IoT) and building automation intertwine more and more these threats are also valid for IoT installations. The paper presents new attack vectors and new threats using the threat model of Meyer et al.[1].

Synthesizing hardware from a Hardware Description Language (HDL) for Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) is very important today because many companies produce ASICs or use FPGAs for prototyping or High Performance Computing (HPC). Although, the synthesis, mapping and routing processes are well understood and good covered by research, some challenges in the operation of these processes exist, such as easy design space exploration, commercial license management, and different software version support which are not focus of research yet. This paper addresses these challenges by proposing the outsourcing of the whole hardware synthesis process into the cloud. A complete cloud-based synthesis service is presented consisting out of a command line client to deploy a synthesis process into the cloud, a remote web-service to schedule synthesis jobs within a cluster of servers or virtual machines, and a control webservice on each of these machines to start and stop the synthesis process. This service is evaluated against the standard local synthesis flow.

Security and privacy are very important assets within building and home automation because the System Control Unit (SCU) stores and processes a huge amount of data about the inhabitants or employees of the building. This data is necessary for managing the building and increasing the convenience of persons within. But this data can also be used to create a movement profile, monitor working times, and draw conclusions about people's health situation. Modern smart home implementations also control many actuators within the building including doors, windows, locks, and fire extinguisher. These increase security and safety, but unauthorized control can reduce the security and can even be harmful to persons. Therefore, identifying the different security and privacy threats is very important and helps system engineers and system managers to develop and deploy secure systems. This work presents an abstract model of a building automation system and some attack trees which simplify threat identification. Attack trees are common in secure software development and secure system deployment. An example smart home deployment is evaluated using the proposed model and attack trees to show the feasibility.

Partial runtime reconfiguration is a feature of modern Field Programmable Gate Arrays (FPGAs). It allows the reconfiguration of some parts of the FPGA, while other parts are still running and doing computations. The design flow to create a partially run-time reconfigurable system includes the partitioning of a FPGA into multiple collaborating Reconfigurable Modules (RMs), as part of the floor-planning design stage, and the development of an interconnection network. The latency of the chosen interconnection network determines the maximum clock speed the components inside the RMs can run at. The customary way of choosing design constraints to achieve the highest possible speed can lead to very long placement and routing times or even to an un-routable design. Eventually, the the Time To Market (TTM) of a product can be inreased. This paper proposes measuring the latencies of the interconnection network after a relaxed configuration phase. This is achieved by configuring two different kinds of components into the RMs and measure the round trip time of the network between them. Thus, the best placement of reconfigurable components, as well as the maximum clock rate of a given configuration can be calculated, and set without the need to rebuild the system. This enables the developer to place components into the RMs according to their clock speed requirements, without the need to reconfigure or rebuild the full system. This paper also presents some example measurements and an example placement of a small microcontroller.

In the past the computer architetures and technologies have only been optimized for speed - never for security. The aspects of IT-security were always disregarded. [1] shows that it is possible to write malware that can not be detected or removed from an infected system by software. Stealth-features are possible by special properties of the x86 architecture. This work describes a general hardware architecture, that will improve the security.