This paper describes the performance pitfalls when using tiered memory for a networked key-value store and our approach to avoiding them. We observe that when receiving data over the network, writing data to tiered memory results in multiple data stagings and repetitive user-kernel crossings. We also observe sudden bursts of I/O operations when allocating memory if the slower memory tier is backed by a DAX file system. We address these challenges through (1) PPF (packet peek and forward) that peeks at the packets in the kernel layer with eBPF and streamlines data placement decisions on tiered memory, and (2) OMA (opportune memory allocator) that moves zeroing off the critical path. Performance evaluation with the prototype shows that the adoption of our design improves IOPS by up to 128%.

This article traces the evolution of SSD (solid-state drive) interfaces, examining the transition from the block storage paradigm inherited from hard disk drives to SSD-specific standards customized to flash memory. Early SSDs conformed to the block abstraction for compatibility with the existing software storage stack, but studies and deployments show that this limits the performance potential for SSDs. As a result, new SSD-specific interface standards emerged to not only capitalize on the low latency and abundant internal parallelism of SSDs, but also include new command sets that diverge from the longstanding block abstraction. We first describe flash memory technology in the context of the block storage abstraction and the components within an SSD that provide the block storage illusion. We then describe the genealogy and relationships among academic research and industry standardization efforts for SSDs, along with some of their rise and fall in popularity. We classify these works into four evolving branches: (1) extending block abstraction with host-SSD hints/directives; (2) enhancing host-level control over SSDs; (3) offloading host-level management to SSDs; and (4) making SSDs byte-addressable. By dissecting these trajectories, the article also sheds light on the emerging challenges and opportunities, providing a roadmap for future research and development in SSD technologies.

We present a framework called Hierarchically Interacting Logs (HIL) for constructing Flash Translation Layers (FTLs). The main goal of the HIL framework is to heal the Achilles heel —the crash recovery—of FTLs (hence, its name). Nonetheless, the framework itself is general enough to encompass not only block-mapped and page-mapped FTLs but also many of their variants, including hybrid ones, because of its compositional nature. Crash recovery within the HIL framework proceeds in two phases: structural recovery and functional recovery. During the structural recovery, residual effects due to program operations ongoing at the time of the crash are eliminated in an atomic manner using shadow paging. During the functional recovery, operations that would have been performed if there had been no crash are replayed in a redo-only fashion. Both phases operate in an idempotent manner, preventing repeated crashes during recovery from causing any additional problems. We demonstrate the practicality of the proposed HIL framework by implementing a prototype and showing that its performance during normal execution and also during crash recovery is at least as good as those of state-of-the-art SSDs.

Flash memory is used as a main data storage medium in increasingly large areas of applications, rapidly replacing hard disk drives because of its low power consumption, fast random access, and high shock resistance. Such flash-based storage devices generally incorporate multiple flash memory chips to meet the ever growing capacity demands. Using multiple chips in a single storage device, at the same time, opens an opportunity to boost the performance based on multi-unit parallelism. However, parallel execution of multiple flash operations introduces complications when bad blocks occur, which is unavoidable due to flash memory’s physical characteristics. The situation gets even worse when bad block occurrences are accompanied by sudden power failures. We propose a bad block management scheme called P-BMS that can fully utilize flash-level parallelism, while guaranteeing provably correct block replacement. Experiments show that our P-BMS achieves a throughput that is more than 95% of the maximum bandwidth of the flash controller, even with bad block occurrences far heavier than in real flash memory.

This tutorial deals with various hardware/software issues in designing and implementing flash memory storage systems. It will be split into three parts - the first part is on flash memory internals and flash memory management software called the flash translation layer, the second on solid state disks that emulate hard disk drives using flash memory, and finally the third on reliability issues arising from various asynchronous/synchronous faults.

Ozone (O3) is a flash memory controller that increases the performance of a flash storage system by executing multiple flash operations out of order. In the O3 flash controller, data dependencies are the only ordering constraints on the execution of multiple flash operations. This allows O3 to exploit the multichip parallelism inherent in flash memory much more effectively than interleaving. The O3 controller also provides a prioritized handling of flash operations, equipping flash management software, such as the FTL (flash translation layer), with control knobs for managing flash operations of different time criticalities. Running a range of workloads on an FPGA implementation showed that the O3 flash controller achieves 3 to 100 percent more throughput than interleaving, with 46 to 88 percent lower response times.

Flash memory solid-state disks (SSDs) are replacing hard disk drives (HDDs) in mobile computing systems because of their lower power consumption, faster random access, and greater shock resistance. We describe Hydra, a high-performance flash memory SSD architecture that translates the parallelism inherent in multiple flash memory chips into improved performance, by means of both bus-level and chip-level interleaving. Hydra has a prioritized structure of memory controllers, consisting of a single high-priority foreground unit, to deal with read requests, and multiple background units, all capable of autonomous execution of sequences of high-level flash memory operations. Hydra also employs an aggressive write buffering mechanism based on block mapping to ensure that multiple flash memory chips are used effectively, and also to expedite the processing of write requests. Performance evaluation of an FPGA implementation of the Hydra SSD architecture shows that its performance is more than 80 percent better than the best of the comparable HDDs and SSDs that we considered.

In this paper, we explain the basics of flash memory technology in general and solid state disks in particular, and describe development platforms specifically designed for flash memory solid state disks.

Flash memory is increasingly being used in embedded systems because of its small size, low power consumption, fast access time, and high shock and vibration resistance. This paper presents a flash memory-based development platform for embedded systems in general and homecare devices in particular, and explains its key features that provide ease and flexibility in exploring cost-performance trade-off in flash memory-based storage devices. In addition to its special emphasis on support for flash memory-based storage, the platform is designed to provide fast prototyping and easy evaluation for a wide range of embedded systems.

This paper reviews Flash memory technology and flash translation layer (FTL) that provides a block device interface out of flash memory. It also describes two implementations of FTL that represent two extreme points in the spectrum of cost-performance trade-offs in FTL implementation. After presenting results on the performance and energy- efficiency of the two FTLs, this paper argues for a configurable FTL to address the diversity of mobile embedded systems in terms of cost and performance requirements.

In this paper, we describe the basics of flash memory technology in general and flash memory drive in particular, and explain the current trends of major components of a flash memory drive including flash memory chips, host interface and flash memory controller.