Nowadays, the reliability in network-on-chip (NoC) has become a crucial issue that leads to network performance degradation. Built-in-self-test (BIST) is one of the primary test schemes often used to achieve high reliability. The scheme allows a frequent test of and recovery from faults experienced on an NoC’s fundamental component, e.g., communication channels. This paper presents a BIST approach that detects open and short faults in communication media to demonstrate the fault-masking phenomenon. The phenomenon as the self-repairing mode of the communication media improves the yield and performance of the NoCs. Rigorous simulations are made on an 8×8 mesh NoC with faulty and repaired channels. Results reveal that allowing faults in communication tracks degrades the network performance up to 30% while the self-repairing mode improves nearly 75%.

Nowadays System on Chip (SOC) is used widely. Clients require gadgets that can handle several applications progressively. Due to an increase in the number of applications, the number of cores embedded in SOC increased too. Each core has a large number of components which increases the probability of occurring of bridging faults in SOC. Efficient testing of these faults is necessary. Testing larger SOC needs large test data volume (TDV), large test access time (TAT). It is hard to store this large amount of test data. It requires a large amount of time to process this test data which makes the testing sluggish. Testing is more complicated for large SOCs. Various traditional methods for testing bridging faults are already proposed to test SOC thoroughly. These strategies are accurate but more expensive in terms of testing resources and the cost of testing. A large number of cores in SOC leads to long TAT which is infeasible sometimes. In this paper, a method is proposed to test the bridging faults and to reduce the TDV and TAT. We propose an efficient method for incomplete testing of SOC considering bridging faults which affectively reduces the TDV but with a little compromise with the fault coverage. In this method, essential bridging faults are considered and a heuristic optimization technique is utilized to improve the TDV while compromising with the quality of testing.

With the continuous growth in wire density, the reliability has become a dominant burden while channels of a modern NoC are exposed to various faults. A key requirement for the NoC is therefore to propose a mechanism that can account for a channel fault since it significantly impacts NoC performance. This paper presents a distributed test strategy that detects and diagnoses logic-level faults coexist in NoC channels and deeply analyze the severe impact of these faults on network performance. Fault coexistence in channels makes a fraction undetectable and is addressed here. Simulation results demonstrate the effectiveness of the proposed strategy.

The reversible logic circuit is a prominent research area for its low-power design, and also quantum computing. The development of synthesis and optimization is a well-known problem in the reversible circuits. For ensuring the high reliability and integrity performance of these circuits, the proper testing technique will be required to detect and locate the faults. In this paper, we consider the problem of reversible circuit testing, specifically targeting the fault detection for the missing-gate fault model in the k-CNOT based reversible circuit. It has been shown that n number of test vectors is sufficient for the detection of all single missing-gate faults (SMGFs), repeated-gate faults (RGFs), and partial missing-gate faults (PMGFs) of the proposed fault detection scheme in a reversible circuit with n inputs. Finally, we provide our experimental results based on several benchmark circuits and also show the comparative analysis with existing methods.

The maximizing yield concept ensures a semi-conductor manufacturing structure towards recognizing, diminishing, and avoiding yield-related defects and contamination. According to the current scenario of technology scaling, manufacturing yield is measured in terms of the number of perfect chips produced. However, in this paper, an imperfect chip producing a good-enough result like Approximate Circuit (AxIC) can also be considered and helps enhance the yield. Hence, this paper's primary objective is to identify those acceptable circuits (AcICs) through retesting, which indirectly increases the effective yield. The basic idea is to divide the testing process into two phases. In the first phase, we follow a conventional test flow architecture and collect the rejected circuits. In the second phase, all the rejected circuits that are tested imperfect in the first phase are retested by applying the test patterns. During this phase, the circuit may produce wrong results for some test patterns, but we should ignore and continue the test until all the test patterns are applied. The test patterns for which the circuit produces a wrong result (error) are quantified and checked against the golden output for deviation. If the amount of deviation is nominal and does not affect the circuit's overall performance, then the circuit is accepted as an AxIC. Though the circuit does not precisely follow the definitions of AxICs, it can significantly contribute to the yield enhancement and termed as AcICs.

High--performance multiprocessor SoCs used in practice require a complex network-on-chip (NoC) as communication architecture, and the channels therein often suffer from various manufacturing defects. Such physical defects cause a multitude of system-level failures and subsequent degradation of reliability, yield, and performance of the computing platform. Most of the existing test approaches consider mesh-based NoC channels only and do not perform well for other regular topologies such as octagons or spidergons, with regard to test time and overhead issues. This article proposes a topology-agnostic test mechanism that is capable of diagnosing on-line, coexistent channel-short, and stuck-at faults in these special NoCs as well as in traditional mesh architectures. We introduce a new test model called Damaru to decompose the network and present an efficient scheduling scheme to reduce test time without compromising resource utilization during testing. Additionally, the proposed scheduling scheme scales well with network size, channel width, and topological diversity. Simulation results show that the method achieves nearly 92% fault coverage and improves area overhead by almost 60% and test time by 98% compared to earlier approaches. As a sequel, packet latency and energy consumption are also improved by 67.05% and 54.69%, respectively, and they are further improved with increasing network size.

This paper presents a fast and low cost on-line scheme named Charka that analyzes short faults in channels of octagon NoCs. Experimental results demonstrate that the proposed scheme achieves 100% coverage metrics and its online evaluation reveals compelling effect of these faults on system performance. We observe that the proposed scheme is upto 9X faster while packet latency is improved by 13.79-21.17% and energy consumption is reduced by 17.57-24.97%. Further, the test area overhead is reduced by 13-26% that shows 52-57.77% improvement.

Packet corruption, misrouting, and dropping have become an extra burden on network performances due to stuck-at and open faults on network-on-chip (NoC) interconnects. Existing works for testing interconnect faults have addressed either shorts and/or stuck-ats with the assumption that the opens do not exist on interconnects. A new distributed test scheme that addresses coexistent stuck-at and open faults on NoC interconnects is proposed. The scheme is governed by a set of odd/even router and cores and takes account of testing of a subset of interconnects in turn. Results achieve 100% fault coverage in terms of packets received and dropped, and test coverage in terms of link-wires tested. Results also show evaluation of different performance metrics affected by the faulty links in a NoC.

This paper presents a scalable time optimized online test solution that addresses short faults in interconnects of an on-chip network (NoC) and observes the deep impact of these faults on NoC performance at large traffics.

Traditional bus-based systems-on-chip (SoCs) are turned to on-chip networks (NoCs) to overcome communication bottleneck. But, fabricating such NoC-based systems without any defect in interconnects or logics is a major challenge. This paper proposes a cost effective and scalable on-line test solution that detects and diagnoses intra-and inter-shorts in NoC interconnects. The proposed solution offers constant test time with general NoC topologies, and channel widths considering little hardware area and performance overheads. Simulation results establish the effectiveness of the proposed solution. We see that the test time is reduced by 0.5-11.25x achieving 100% coverage metrics. Simulation results also reveal the significant effect of interconnect shorts on network performance at large traffics. We see that our test solution improves packet latency by 14.98-40.57% and reduces energy consumption of a packet flit by 6.83-31.19%.

In an on-chip network (NoC), the channels often experience several open faults because of certain manufacturing or in-field defects. Such faults may cause enormous loss of packets degrading the reliability and performance of the system. A reliability-aware NoC should include a module that has the capability of detecting and locating an open fault in the channels so as to enable alternative routing paths and to prevent excessive packet loss. This paper proposes an on-line test scheme that detects open faults and locates the faulty channel-wires in an NoC. The proposed scheme makes use of diagonal-driven test strategy and scales well when the size of the NoC increases. We evaluate the performance of an NoC under large-traffic scenario and our simulation results establish the effectiveness of the proposed scheme in terms of several network-metrics.

The presence of open-faults in NoC channels drastically drops packets while routing them causing severe degradation of network performance. Nevertheless, it can still be compensated by utilizing a fault-repairing scheme. This paper shows how the performance of a NoC architecture can be improved through self-repairing of open channels using short-defects. Simulation results reveal that the performance degrades to nearly 30% when the channels suffer from manufacturing open-faults, and to 10% when they are self-repaired with the help of co-existent short-defects. Thus, the overall performance can be improved beyond 65%.

With the ever-shrinking global geometries on a die and the concomitant rise in the complexity of interconnections in an on-chip network (NoC), the links used therein often suffer from various manufacturing defects such as shorts. These defects not only cause logical or functional errors but also give rise to various other system level failures such as duplication, misrouting, or dropping of a packet, thereby impacting the performance of the network significantly. This paper proposes an on-line test method that detects the presence of pairwise-shorts, if any, and identifies the faulty links. Several performance metrics are evaluated to demonstrate the impact of these faults, and simulation results demonstrate 100% coverage. The proposed method scales well to large-size NoCs irrespective of the topology and link-width.

This paper presents a distributed on-line test mechanism that detects stuck-at faults (SAFs) in the channels as well as identifies the faulty channel-wires in an on-chip network (NoC). The proposed test mechanism improves yield and reliability of NoCs at the cost of few test clocks and small performance degradation. Additionally, the mechanism is scalable to large-scale NoCs. We study the impact of channel stuck-at faults on various performance metrics and simulation results establish 100% coverage metrics and the effectiveness of the proposed test mechanism.

Previous works on detecting and locating manufacturing faults-shorts, stuck-at, and open on an interswitch link of a channel in a network-on-chip (NoC) have been based on the assumption that these faults do not coexist. The works failed to diagnose all these faults when this assumption is relaxed. A deficiency for non-diagnosability of these faults is then represented. A packet address driven test strategy that detects and locates a faulty inters witch link in a NoC channel is proposed. The strategy addresses the intra-channel shorts, stuck at, and open faults coexist on inters witch links and is governed by parallel activation of diagonal routers. The strategy is scalable with mesh NoCs. Simulation results achieve 100% and more than 97% fault coverages when faults are diagnosed explicitly and implicitly respectively.

In this paper we propose a high level test pattern generation scheme for integrated circuits designed at the behavioral level. The scheme is based on the directed symbolic execution that results a symbolic expression for a test path. A test pattern for a circuit under test is derived from actual values of input variables on evaluation of the resulting symbolic expression of a test path and ensures the design correctness. The derived test patterns are further used to measure the percentage of design correctness that directs us to code coverage analysis. We achieve 100% code coverage. Experiments are performed on a number of custom-built and benchmark circuits to validate the proposed test generation. The results from the experiments show as well the performance of the proposed scheme.

This paper deals with a branching time temporal query language called Min-max CTL which is similar in syntax to the popular temporal logic, CTL according to E. M. Clarke (1986). Min-max CTL can express timing queries on a timed model, whereas CTL is used for untimed systems. Interesting timing queries involving a combination of min and max can be expressed in Min-max CTL. While model checking using most timed temporal logics is PSPACE complete or harder described by R. Alur and T. A. Henzinger (1993) and R. Alur et al. (1993), it is shown in the work of P. Dasgupta et al. (2001) that many practical timing queries, where we are interested in the worst case or best case timings, can be answered in polynomial time by querying the system using Min-max CTL. In this paper, the syntax of Min-max CTL is extended to increase the expressive power of Min-max CTL.

We propose a new style of model checking of timed transition systems, where instead of reasoning about the timing of states with specific properties, we reason about the timings of events with specific properties. This shift in paradigm appears to be useful for verification of edge triggered control paths, where we are more interested in the timings of changes in signal values. We propose a temporal logic, event-triggered timed computation tree logic (ETCTL), which allows the specification of event properties such as posedge(signal) and negedge(signal) along with real time computation tree logic (RTCTL) properties. We show that all ETCTL properties are interval independent, that is, their truth can never change on states between successive events. By virtue of the interval independent property, reasoning about timings of events (using ETCTL) is more efficient computationally than reasoning about general timed properties. We present a labeling algorithm, and suggest extensions to automata theoretic and symbolic approaches.