As CMOS technology scales down, the number of standard cells increases rapidly. The increasing cell count raises the complexity of physical design. Routing is one of the most time-consuming stages in the physical design flow. When routing fails to meet design rules or performance targets, designers must revise earlier stages such as floorplanning or placement. Repeating the routing process causes high design cost and long time-to-market. Early prediction of routing demand helps reduce design iterations. An ensemble learning model based on XGBoost is proposed to predict global routing demand using placement-stage features. The XGBoost-based model achieves higher accuracy than CNN- and FCN-based models, improving R² by 0.12 and 0.125, respectively. The inference speed is also significantly faster, up to 14.95×. Feature importance analysis enables reduction of training and inference overhead with minimal accuracy loss.

This study introduces an Automatic Personality Recognition (APR) model, named XLNet refined-highway-switch network, comprising XLNet, refined highway units, a switching module, and a fully-connected layer. The pretrained XLNet is employed to extract semantic features from text. The refined highway units with the dense connections are explored. Additionally, our study delves into the optimized computation structures between the refined highway and switching module to unearth personality- related features. Notably, this APR model incorporates punctuation and stop words in text, resulting in a notable accuracy boost of up to 6.79%. Through extensive experiments on the integrated datasets which combine My Personality, Essays, and Friends Persona, the proposed model achieves the best average accuracies of64.79% and 64.43% for Big-5 personality traits on English and Chinese versions, respectively, as compared to conventional models. Furthermore, we implemented the proposed APR model in a retrieval-based chatbot, utilizing Jaccard distance to select the most suitable personality responses for interactions, yielding promising results in subject tests. Consequently, the proposed APR model can be widely used in various personalized applications related to personality traits.

Register clustering is an effective technique for suppressing the increasing dynamic power ratio in modern IC design. By clustering registers (flip-flops) into multi-bit flip-flops (MBFFs), clock circuitry can be shared, and the number of clock sinks and buffers can be lowered, thereby reducing power consumption. Recently, the use of mixed-driving strength MBFFs has provided more flexibility for power and timing optimization. Nevertheless, existing register clustering methods usually employ evenly distributed and invariant path slack strategies. Unlike them, in this work, we propose a register clustering algorithm with slack redistribution at the post-placement stage. Our approach allows registers to borrow slack from connected paths, creates the possibility to cluster with neighboring maximal cliques, and releases extra slack. An adaptive interval graph based on the red-black tree is developed to efficiently adapt timing feasible regions of flip-flops for slack redistribution. An attraction-repulsion force model is tailored to wisely select flip-flops to be included in each MBFF. Experimental results show that our approach outperforms state-of-the-art work in terms of clock power reduction, timing balancing, and runtime.

Design Rule Checking (DRC) is one of the most important metrices in physical design procedure to evaluate quality of a detail route. The prediction of DRC violation (DRV) in the early stage can reduce the iterations of design procedure and improve the efficiency of the physical design closure. Several researchers have applied machine-learning techniques to predict the DRVs of a detail route at different design stages with various input features. In this paper, we proposed a machine learning model to predict DRVs with the information obtained after placement stage. Specifically, we build a ResNet-like CNN model to predict whether a DRV may occur in a targeted grid after detail route. Our features consist of not only quantified placement information but also layout-image features to take pin accessibility into account for better prediction result. Moreover, we apply an under-sampling technique to select critical training samples to improve the training efficiency. A series of experiments have been conducted and the results show that compared with previous works, our prediction result can outperform Fully Convolutional Network (FCN) based approaches.

Design rule checking (DRC) violation (DRV) prediction with early stage design information can help to reduce the iterations of design procedure and can speed up the physical-design closure. It is known that accurately predicting detailed routing-level DRV with information obtained at global route (GR) stage can significantly speed up the design closure. However, without sufficient prediction accuracy, the result may lead to suboptimal design or even longer design time. Therefore, in this article, we propose two machine-learning frameworks to predict the detailed routing-level DRV map of a given design. The first framework is based on the congestion report obtained at global routing stage, and the second framework considers both the placement information and the congestion report of global routing. We then compare the runtime and accuracy of the two models. The proposed frameworks utilize convolutional neural network as the core technique to train these prediction models. The training dataset is collected from 15 industrial designs using a leading commercial automatic placement and routing (APR) tool, and the total number of collected training samples exceeds 26M. A specialized under-sampling technique is also proposed to select important training samples for learning, compensate for the inaccuracy misled by a highly imbalanced training dataset, and speed up the entire training process. The experimental results demonstrate that our both models can result in not only a significantly higher accuracy than previous related works, but also a DRV map visually matching the actual ones closely. The average runtime of using our learned model from the first framework to generate a DRV map is only 3% of global routing, and the prediction accuracy of our learned model from the second framework can improve 7.6% compared to the one from the first framework. Our proposed framework can be viewed as a simple add-on tool to a current commercial placement and global router that can efficiently and effectively generate a more realistic DRV map without really applying detailed routing.

Excessive dynamic IR-drop degrades the circuit performance and may lead to functional failure. Existing IR-drop fixing techniques at the placement stage do not consider the time-variant property and thus cannot handle dynamic IR-drop hotspots well. In current practice, designers perform Engineer Change Order (ECO) to move out these hotspot cells based on their experience. In this paper, we present a novel dynamic IR-drop ECO optimization and prediction framework by wise cell movement. We first spread high demand current cells in a global view to stagger their current waveforms. Then, we further move IR hotspot cells close to power/ground (PG) vias for minimizing the resistance from PG pads to their PG pins. Moreover, we propose an accurate machine learning-based dynamic IR-drop prediction model to guide the final cell movement. The features of our model capture power ground network characteristics, timing information, and cumulative current drawn by cells, thus leading to a general model applicable to ECO. Experimental results show that our proposed model precisely predicts dynamic IR-drop after cell movement, and our optimization scheme can substantially alleviate dynamic IR-drop without timing degradation.

In this paper, we have proposed a machine-learning framework to predict the DRC-violation map of a given design resulting from its detailed routing based on the congestion report resulting from its global routing. The proposed framework utilizes convolutional neural network as its core technique to train this prediction model. The training dataset is collected from 15 industrial designs using a leading commercial APR tool, and the total number of collected training samples exceed 26M. A specialized under-sampling technique is proposed to select important training samples for learning, compensate for the inaccuracy misled by a highly imbalanced training dataset, and speed up the entire training process. The experimental result demonstrates that our trained model can result in not only a significantly higher accuracy than previous related works but also a DRC violation map visually matching the actual ones closely. The average runtime of using our learned model to generate a DRC-violation map is only 3% of that of global routing, and hence our proposed framework can be viewed as a simple add-on tool to a current commercial global router that can efficiently and effectively generate a more realistic DRC-violation map without really applying detailed routing.

As technology node keeps scaling and design complexity keeps increasing, power distribution networks (PDNs) require more routing resource to meet IR-drop and electro-migration (EM) constraints. This paper presents a design flow to generate a PDN that can result in near-minimal overhead for the routing of the underlying standard cells while satisfying both IR-drop and EM constraints based on a given cell placement. The design flow relies on a machine-learning model to quickly predict the total wire length of global route associated with a given PDN configuration in order to speed up the search process. The experimental results based on various 28 nm industrial block designs have demonstrated the accuracy of the learned model for predicting the routing cost and the effectiveness of the proposed framework for reducing the routing cost of the final PDN.

As technology node keeps scaling and design complexity keeps increasing, power distribution networks (PDNs) require more routing resource to meet IR-drop and EM constraints. This paper presents a design flow to generate a PDN that can result in minimal overhead for the routing of the underlying standard cells while satisfying both IR-drop and EM constraints based on a given cell placement. The design flow relies on a machine-learning model to quickly predict the total wire length of global route associated with a given PDN configuration in order to speed up the search process. The experimental results based on various 28nm industrial block designs have demonstrated the accuracy of the learned model for predicting the routing cost and the effectiveness of the proposed framework for reducing the routing cost of the final PDN.

We present our experience of DFM (design for manufacturability) and DFY (design for yield) considerations on physical designs at 0.13 mum and below technology nodes. The impact of some DFM approaches on timing and signal integrity are addressed. We also present our experience of yield analysis and improvement for the designs with process variation and dynamic IR drop issues.