A new design methodology for reducing the area and power of standard cell ASICs that uses a combination of differential flipflops and a method of deliberate clock-skewing, called local clocking (LC), is described. LC introduces clock skew without the use of extra buffers in the clock network. This is done by having some flipflops, called sources, generate clock signals for other flipflops, called targets. The method involves two key features: 1) the design of a new differential flipflop, referred to as KVFF, that is functionally identical to a double-latch edge-triggered$D$flipflop, but in addition, produces a completion signal that is a skewed version of its input clock, which is used to clock other flipflops and 2) an efficient algorithm that identifies the sources and targets involved in the new clocking scheme, with the objective of reducing area and power. These are reduced because deliberate skew introduces extra slack on the logic cones that feed the target flipflops, which is exploited by synthesis tools to reduce area and power. Furthermore, the area and power overhead of conventional methods of introducing skew, e.g., buffers, is eliminated. LC is shown to result in significant improvements in area, power, and wirelength for several, publicly available, benchmark circuits for 65 nm bulk CMOS and 28 nm FDSOI technologies. For 65 nm, the average improvement in area, power and wirelength were 27.7%, 13.4%, and 21.0%, respectively. For 28 nm FDSOI the average improvement in area, power, and wirelength were 20.0%, 10.5%, and 30.5%, respectively. In addition, this article demonstrates how LC can be used to eliminate hold time violations.

A new method for reducing power and area of standard cell ASICs is described. The method is based on deliberately introducing clock skew without the use of extra buffers in the clock network. This is done by having some flipflops, called sources, generate clock signals for other flipflops, called targets. The method involves two key features: (1) the design of new differential flipflop, referred to as KVFF, that is functionally identical to a master-slave edge-triggered D flipflop, but in addition, produces an completion signal that is a skewed version of its input clock, which is used to clock other flipflops; and (2) an efficient algorithm that identifies the sources and targets involved in the new clocking scheme, with the objective of reducing area and power. These are reduced because deliberate skew introduces extra slack on the logic cones that feed the target flipflops, which is exploited by synthesis tools to reduce area and power. In addition, the overhead of conventional methods of introducing skew, e.g. buffers, is eliminated. Using commercial tools, significant improvements in power and area are shown on placed and routed netlists of several circuits.

In this paper, we describe a new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits, without sacrificing performance. The approach is based on a design of threshold logic gates (TLGs) and their seamless integration with conventional standard-cell design flow. We first describe a new robust, standard-cell library of configurable circuits for implementing threshold functions. Abstractly, the threshold gate behaves as a multi-input, single-output, edge-triggered flip-flop, which computes a threshold function of the inputs on the clock edge. The library consists of a small number of cells, each of which can compute a set of complex threshold functions, which would otherwise require a multilevel network. The function realized by a given threshold gate is determined by how signals are mapped to its inputs. We present a method for the assignment of signals to the inputs of a threshold gate to realize a given threshold function. Next, we present an algorithm that replaces a subset of flip-flops and portions of their logic cones in a conventional logic netlist, with threshold gates from the library. The resulting circuits, with both conventional and TLGs (called hybrid circuits), are placed and routed using commercial tools. We demonstrate significant reductions (using postlayout simulations) in power, leakage, and area of the hybrid circuits when compared with the conventional logic circuits, when both are operated at the maximum possible frequency of the conventional design.

This article explores the use of threshold logic for reducing the power, delay, and/or area of digital logic circuits. We first describe the architecture of a differential threshold logic gate (TLG) using conventional MOSFETs. A TLG of a given number of inputs can be configured to realize a set of threshold functions by simply connecting the appropriate signals to its inputs. One characteristic of the proposed architecture for a TLG is the increased sensitivity to process variations (device mismatch) and noise. Problems due to device mismatch can be mitigated by proper cell design and optimization. The increased sensitivity to noise makes it difficult to scale the supply voltage of a TLG. We show a simple solution which involves integrating RRAMs within the TLG circuit, to achieve robust, low voltage and energy efficient operation. The third circuit implementation referred to as a spintronic threshold logic (STL) cell uses an STT-MTJ device as a intrinsic threshold logic gate. An STL cell is an very compact structure that can realize a large number of threshold functions, many of which would require a multilevel network of conventional CMOS logic gates.

In this paper, we describe two single input threshold gate (TLG) designs, which are functionally equivalent to differential flipflops. We present a detailed comparison of TLGs with two well established D-flipflop designs. The comparisons are done in both 65nm and 28nm commercial processes. We compare total delay, which is defined as the sum of setup delay and clock to output delay. We also show a comparison of tolerance against noise and process variation between the different designs. The two proposed designs are found to be as robust as an existing D-flipflop from both commercial standard cell libraries. Meanwhile, they are 33% and 25% faster in 65nm post-layout and 25% and 22% faster in 28nm post-layout compared to a commercial D-flipflop. The energy delay product of two proposed designs is 46% and 25% smaller in the 28nm process post layout simulation. Single input threshold gates can also be extended to multi-input threshold gates. We compare the total delay, power and leakage of a three-input threshold gate as well as a seven-input threshold gate with those of the equivalent (Complementary Metal Oxide Semiconductor) CMOS counterpart, which shows 52% 48% improvement in 65nm and 35% speed improvement in the 28nm process.

Threshold-logic gates have long been known to result in more compact and faster circuits when compared to conventional AND/OR logic equivalents [1], However, threshold logic based design has not entered the mainstream design technology (neither custom ASIC nor FPGA) due to the lack of efficient and reliable gate implementations and the necessary infrastructure for automated synthesis and physical design. This paper is a step toward addressing this gap. We present the architecture of a novel programmable logic array, referred to as Field Programmable Threshold-Logic Array (FPTLA), in which the basic cells are differential mode threshold-logic gates (DTGs). Each individual DTG cell is a clock edge-triggered circuit that computes a threshold-logic function. A DTG can be programmed to implement different threshold logic functions by routing appropriate signals to their inputs. This reduces the number of SRAMs inside the logic blocks by about 60% compared to conventional CLBs, without adding any significant overhead in the routing infrastructure. Since a DTG is essentially a multi-input, edge-triggered flipflop that computes a threshold function, a network of DTGs forms a nano-pipelined circuit. The advantages of such a network are demonstrated on a set of deeply pipelined datapath circuits implemented on FPTLAs and conventional FPGAs using the well established FPGA design framework VTR (Verilog To Routing) and VPR (Versatile Place and Route) [2]. The results indicate that an FPTLA can achieve up to 2X improvement in delay for nearly the same energy and logic area compared to the conventional LUT based FPGA. Although differential mode circuits can potentially be more sensitive to process variations, FPTLAs can be made robust to such variations without sacrificing their improved energy efficiency and performance over FPGAs.

This paper describes the design of a standard cell library of differential mode threshold gates, referred to as a Threshold Logic Latch or TLL, and new threshold function identification and decomposition methods to map a conventional logic network consisting of logic gates and flipflops, into a hybrid network that consists of both TLLs and conventional logic gates. After logic synthesis and physical design (placement and routing) using a commercial 65nm LP (low power) library, and commercial design tools, the hybrid circuits are shown to have up to 35% less dynamic power, about 50% less leakage power and around 37% less area when compared to the corresponding conventional design operated at the same (peak) frequency.

This paper presents a new and efficient heuristic procedure for determining whether or not a given Boolean function is a threshold function, when the Boolean function is given in the form of a decision diagram. The decision diagram based method is significantly different from earlier methods that are based on solving linear inequalities in Boolean variables that derived from truth tables. This method's success depends on the ordering of the variables in the binary decision diagram (BDD). An alternative data structure, and one that is more compact than a BDD, called a max literal factor tree (MLFT) is introduced. An MLFT is a particular type of factoring tree and was found to be more efficient than a BDD for identifying threshold functions. The threshold identification procedure is applied to the MCNC benchmark circuits to synthesize threshold gate networks.