This article presents adiabatic data transmitters using stepwise driving to improve the energy efficiency of low data-rate sensor nodes beyond theCV2limitation. Stepwise driving is applied to NRZ and PAM-4 modulations, supporting data rates of hundreds of Mb/s, required by micro-controller peripheral I/O interfaces in sensor nodes. Fabricated in 22nm CMOS, the proposed transmitter drivers achieve over 64% energy savings at 200 Mb/s compared to conventionalCV2drivers.

In this paper, we propose an output-capacitorless analog low-dropout voltage regulator (ALDO) featuring frequency compensation of a four-stage amplifier consisting of a three-stage error amplifier (EA) without cascoding plus a last stage formed by a pass transistor ($\boldsymbol {M_{P}}$). It achieves good output voltage regulation under low supply-voltage ($V_{dd}$) with an unsaturated$\boldsymbol {M_{P}}$(e.g., dropout voltage of 30 mV under 0.5 V supply) because of the three gain stages in the EA. Frequency compensation is achieved by performing a two-port feedback analysis with the root-locus diagram (TFR) method that provides an intuitive understanding of pole/zero dynamics in the$s$-plane. Fabricated in 0.18$\mu \text{m}$CMOS, the proposed ALDO achieves asymptotic stability over a wide range of operating conditions:$V_{dd}$of$0.5\sim 1.8$V, load capacitance of 0~50 pF, load current ($I_{L}$) of 0~2 mA (0~200 mA) under$V_{dd}$of 0.5 V (1.8 V), and temperature of$- 20\sim 125\,\,^{\circ }\text{C}$. Also, it does not require minimum on-chip output capacitance, thus achieving a small area of 0.0035 mm2. As a result, a good low-frequency PSR of −62 dB with a dropout voltage of 30 mV and a state-of-the-art current density of 11.4 A/mm2 are achieved.

In this paper, we analyze faradaic DC current (FC) generated by inherent offset charge (IOC) and charge mismatch. Under frequent shorting, the analysis shows that mismatch- induced DC current is small compared to IOC-induced DC current. To reduce the FC, we propose a biphasic pulse scheme which compensates the IOC. Simulation results show the proposed pulse scheme reduces the FC by about 58 times compared to a conventional biphasic pulse.

This paper presents a sensor front-end for air pressure sensor, relative humidity (RH) sensor, and accelerometer in a standard CMOS process. For air pressure and RH, interdigitated top metals in air and polyimide are exploited respectively, which exhibit the change in dielectric constant. For acceleration, separation among three bondwires is exploited. These sensing transducers induce capacitance change that is quantized by a CDC based on a dual quantization architecture that employs a single-bit 1st-order ΔΣ modulator and a 7-bit SAR ADC.

In this paper, we present a supply noise insensitive phase-locked loop using a wideband noise suppression loop around the oscillator. The proposed approach suppresses supply noise without reducing the voltage headroom of the oscillator and does not require any calibration or additional settling time for noise suppression. The proposed PLL is implemented in 65nm CMOS, achieving an average spur suppression of 30dB near PLL loop bandwidth, while consuming 2.73mW at the 3.2GHz output.

A zero-crossing-based circuit (ZCBC) is a promising technique for low-power high-resolution pipeline analog-to-digital converters (ADCs). Unfortunately, operating ZCBC ADCs at high speeds near 1 GS/s is quite challenging due to the delay of the zero-crossing detector that introduces nonlinear gain and offset errors. To solve nonlinearity, we propose a ZCBC pipeline ADC that employs a passive resistor as a current source. Due to its inherent linearity, the resistor-based ZCBC eliminates the input dependency of the interstage gain and offset errors, allowing a simple calibration. Furthermore, a background offset calibration scheme is proposed to cope with the large offset that results from high-speed operation. A prototype ADC implemented in 65-nm CMOS achieves an SNDR/SFDR of 47.26/62.64 dB at 1 GS/s while consuming 46.52 mW from 1 V supply.

A first-order time-based ΔΣ modulator using voltage-controlled oscillator (VCO) is presented. The proposed modulator employs phase interpolation technique to enhance the time resolution of the VCO and digital calibration to improve the linearity of the VCO tuning curve. The proposed modulator, implemented in 0.13 μm CMOS process, achieves 55 dB peak signal-to-noise ratio and 52.5 dB peak signal-to-noise-and-distortion ratio at 600 MHz sampling frequency for 20 MHz input bandwidth and consumes 14.3 mW.

This paper presents a digitally controlled injection-locked multimodulus frequency divider (ILMFD) based on a ring-oscillator using inverter chains for a small area and low power consumption. In the proposed ILMFD, division ratios of 2, 3, 4, 5 and 6 are achieved by using a programmable delay line that changes the self-oscillation frequency of the ring-oscillator. The locking range of the proposed ILMFD is improved by employing a dual-input injection scheme, which unlike previous multiinput injection schemes, does not require distinct phase inputs. A prototype chip implemented in a 0.13-$\mu{\hbox {m}}$CMOS process has an area of$35\times 33\ \mu{\hbox {m}}^{2}$and operates at 5 GHz while consuming 470$\mu{\hbox {W}}$from 1.2 V supply, where 350$\mu{\hbox {W}}$is dissipated in the core of the ILMFD. The proposed divider is the first reported multimodulus ILFD with digitally controlled division ratios and an in-phase dual-input injection scheme.

A 10-bit 300 MSample/s pipelined analog to digital converter (ADC) using time-interleaved successive approximation register (SAR) ADC in the first stage is presented. By replacing the front-end pipelined stages with energy-efficient SAR-ADC, power hungry sample-and-hold amplifier can be removed and rail-to-rail input can be used. In addition, feedback factor of the first MDAC can be increased, which significantly reduces the power consumption of the first opamp. Simulation results in 90 nm CMOS show that 8.88 bits of effective-number-of-bits at 300 MHz sampling rate can be achieved while consuming 77mW at 1.2V supply. Figure-of-merit of the proposed ADC is 545fJ/Conv, which is one of the lowest among the recently reported ADCs that achieve 10-bit resolution with sampling rates of hundreds of mega-hertz.

This paper presents a low noise fractional-N PLL that employs the reference multiplication technique. In order to reduce the noise from ΔΣ modulator (DSM) and charge-pump (CP), the proposed PLL increases the OSR of the DSM and reduces the gain of the CP to the output It employs dual phase detector (PD) architecture that can obtain the information of the phase error twice more frequently than a conventional PLL. The prototype chip implemented in 0.13 μm CMOS process achieves 3 dB and 9 dB improvement of phase noise at 10 kHz and 2 MHz offset respectively. It consumes 4.2 mW at 1.2 V supply and occupies 0.23 mm2which are 15 % and 4 % increased in power and area respectively compared to the conventional PLL.

This paper presents an ADPLL using a background KDCOcompensation technique to achieve PVT tolerant loop bandwidth and damping factor over a broad tuning range using a linear averaging estimation of KDCO. Simulation results show that the proposed ADPLL achieves output frequency range from 1GHz to 4.5GHz and the reference frequency range from 10MHz to 80MHz with a constant damping factor and the bandwidth to the reference frequency ratio determined by the digital loop filter.

Continuous monitoring of cardiovascular system can prevent death and disabilities due to heart failure. In this paper, a bio-impedance measurement system that operates on a small local area of the forearm is presented for portable and continuous monitoring of the heart rate and pulse wave velocity (PWV). The impedance variation caused by the heart pump is measured by analog circuitries that consist of amplifiers, mixers and filters. The overall gain, CMRR, and input impedance of the implemented system using discrete components are 80 dB, 72 dB and 477 kOmega at 100 kHz, respectively, which results in a system sensitivity of 21 V/Omega. Experimental results show that the heart rate and PWV can be measured by using only 1.5 cm times 7 cm area of the body. The measured heart rate is in the range of 65~110 beats/min, and PWV is in 6.51 plusmn 2.39 (m/s), which fits well with a reference device and normal physiological range. The optimum location for small electrodes in terms of signal quality is also investigated, and the results show that the location at the lower forearm along the radial artery has the best signal quality.

In this paper, a ring oscillator-based CMOS temperature sensor with nano-watt power consumption is presented for RFID applications. Unlike conventional temperature sensors based on bandgap reference and ADC that consume large amount of power, the proposed sensor exploits the temperature dependence of the threshold voltage and carrier mobility of MOS transistors that affect the frequency of a ring oscillator. In order to maximize the temperature sensitivity and dynamic range, a supply voltage of 0.3 V is used, which allows the oscillator to operate in subthreshold, near-threshold and above threshold region under different temperature conditions. In order to handle process variation, the frequency of the oscillator can be digitally trimmed by both a capacitor bank and stacked transistors. Measured data from 0.13-mum CMOS test chips indicate that the proposed temperature sensor has a resolution of 0.4degC/LSB with a 10-bit digital output code over a temperature range of 8degC to 85degC. At 10 Hz of sampling frequency, the proposed sensor consumes 95 nW and occupies 0.04 mm2.

In this paper, an ultra low power front-end circuit for an UHF RFID tag is presented. In order to minimize the power consumption, a novel data decoder is proposed, which removes the need for high frequency oscillator. In addition, a dual voltage multiplier scheme is employed, which increases the power efficiency. Simulation results shows that the proposed circuit reduces the power consumption by an order magnitude compared to conventional RFID front-end circuits that use high frequency oscillators and single voltage multiplier.

A time-based analog-to-digital converter(ADC) employing a multi-phase voltage-controlled oscillator(VCO) is presented. The VCO is based on a ring oscillator which converts analog input voltage to phase information. Digital output is produced by a phase quantizer which consists of a counter for coarse quantization and phase detector for fine quantization. Using this technique, an 8-bit 100Msamples/s ADC is designed and simulated. Impact of jitter and VCO linearity on the ADC performance is analyzed and verified.

A power-optimized low-voltage VCO with wide tuning range is proposed. The VCO achieves low power by optimum selection of inductance in the L-C tank. Despite the low power supply near threshold voltage, the VCO achieves wide tuning range by using a voltage-boosted digital tuning technique. It is shown that the power consumption of VCO with a required output swing and phase noise can be minimized if the inductance is chosen such that it's LQ and Q/L is maximized. To increase the tuning range, a digital tuning method is used where the output voltage of the VCO is exploited to generate a high voltage for the switches in the digital tuning scheme. The proposed VCO achieves phase noise of -120 dBc/Hz at 1-MHz offset and 18 % tuning range while consuming 660 /spl mu/A in 0.5-V supply. Figure-of-merit with tuning range of the proposed VCO is -197.1 dB, which is the lowest among the recent state-of-the-art low-voltage VCOs.

This paper presents a novel continuous-phase phase-shift-keying (CP-PSK) modulation scheme and a low-power quadrature modulation architecture. In the proposed modulation scheme, phase-shift occurs in a smooth, continuous manner so that it can be implemented using an indirectly modulated frequency synthesizer. In the proposed transmitter architecture, low-power and low-complexity are achieved by employing two indirectly modulated synthesizers for the I and Q paths, thereby eliminating the need for mixers and digital-to-analog converters (DACs). Simulation results show that the bit error rate (BER) and the spectral efficiency of the proposed methods are close to those of ideal PSK modulation schemes

Increasing the lifetime of wireless sensors is essential for the proliferation of wireless sensor networks in various environments. In this paper, the relationship between bandwidth and energy consumption is exploited to increase the lifetime of the sensors. A variable bandwidth allocation scheme that uses time-frequency slot assignment is proposed to reduce the energy consumption of a collaborative sensor network which has large spatial variation in node density and event rates. To assign the time-frequency slots to the sensor network, a novel algorithm is presented, which results in significant energy savings over the conventional constant bandwidth allocation scheme.