Since the design and manufacturing of semiconductor chips takes a considerable amount of time, it is difficult to fully understand the entire process and conduct student experiments that provide a hands-on experience of chip creation. The lack of student experiments that allow beginners to easily experience the process from chip design to manufacturing is one of the reasons why there are few students interested in semiconductor research. This, in turn, exacerbates the shortage of skilled workers in the semiconductor industry. The Agile-Chip platform is a method that enables the rapid and low-cost production of small quantities of chips by manufacturing only the top wiring layer using minimal fab technology on cut wafers, which are pre-cut from mass-produced wafers except for the top-most wiring. In this paper, we propose a student experiment method for semiconductor beginners using the Agile-Chip platform and provide an implementation example. For the base chip, a gate array is used, which allows the configuration of various gates using only the top wiring layer. The students design a 61-stage ring oscillator using the gate array, verify its operation through simulation, and then proceed with the corresponding layout design. After confirming the consistency of both, they generate a GDS file. This wiring layer is then fabricated either in a minimal fab or a cleanroom, and finally, the chip is mounted on a substrate for measurement.

Scaling to finer CMOS process nodes necessitates more masks, resulting in higher costs and extended turnaround times (TATs). High costs and long TATs have hindered researchers outside the field of integrated circuits, including those in medicine, physics, and science from prototyping their own chips. Therefore, opportunities for diverse innovations in integrated circuits and talent development have been limited. We have developed the Agile-X platform for low-cost, rapid manufacturing of system-on-chips. Users can implement their own dedicated circuits with gate-array circuits on a base chip, which has common intellectual properties (IPs) such as RISC-V CPUs, various IOs, and ADCs. The base chip is manufactured in a foundry up to the intermediate metal layers and shipped with metal deposition on its surface. By directly drawing wiring patterns on this base chip with a mask-less lithography system, custom chips can be manufactured on-site without masks. As this process only requires wiring and eliminates masks, production time is drastically reduced compared to traditional full-mask wafer processes and multiproject wafer (MPW) shuttles. Development and manufacturing costs for the base chip, including preintegrated IPs, are shared among all Agile-X users. This reduces both IP and base-chip wafer costs per user. We prototyped wafers using a 0.18-$\mu $m CMOS process and tested the proposed structured ASIC platform and manufacturing process using mask-less lithography systems. The results indicate that the process from inputting GDS data to lithography and dry etching can be completed within 30 min, and custom application-specific integrated circuits (ASICs) can be manufactured within a day. Compared with full-mask wafer design and manufacturing, the manufacturing cost per chip, including IP costs, is reduced from 271000 USD to 22 USD, a reduction of 1/12252, and the manufacturing period is reduced from 20 days to 30 min, a reduction of 1/960.

In modern materials science, effective and high-volume data management across leading-edge experimental facilities and world-class supercomputers is indispensable for cutting-edge research. However, existing integrated systems that handle data from these resources have primarily focused just on smaller-scale cross-institutional or single-domain operations. As a result, they often lack the scalability, efficiency, agility, and interdisciplinarity, needed for handling substantial volumes of data from various researchersIn this paper, we introduce ARIM-mdx data system1, aiming at a nationwide data platform for materials science in Japan. Currently in its trial phase, the platform has been involving 11 universities and institutes all over Japan, and it is utilized by over 800 researchers from around 140 organizations in academia and industry, being intended to gradually expand its reach. The ARIM-mdx data system, as a pioneering nationwide data platform, has the potential to contribute to the creation of new research communities and accelerate innovations.

Aiming at efficient data condensation and improving accuracy, this paper presents a hardware-friendly template reduction (TR) method for the nearest neighbor (NN) classifiers by introducing the concept of critical boundary vectors. A hardware system is also implemented to demonstrate the feasibility of using an field-programmable gate array (FPGA) to accelerate the proposed method. Initially, k -means centers are used as substitutes for the entire template set. Then, to enhance the classification performance, critical boundary vectors are selected by a novel learning algorithm, which is completed within a single iteration. Moreover, to remove noisy boundary vectors that can mislead the classification in a generalized manner, a global categorization scheme has been explored and applied to the algorithm. The global characterization automatically categorizes each classification problem and rapidly selects the boundary vectors according to the nature of the problem. Finally, only critical boundary vectors and k -means centers are used as the new template set for classification. Experimental results for 24 data sets show that the proposed algorithm can effectively reduce the number of template vectors for classification with a high learning speed. At the same time, it improves the accuracy by an average of 2.17% compared with the traditional NN classifiers and also shows greater accuracy than seven other TR methods. We have shown the feasibility of using a proof-of-concept FPGA system of 256 64-D vectors to accelerate the proposed method on hardware. At a 50-MHz clock frequency, the proposed system achieves a 3.86 times higher learning speed than on a 3.4-GHz PC, while consuming only 1% of the power of that used by the PC.

An analog focal-plane processor having a 128128 photodiode array has been developed for directional edge filtering. It can perform 44-pixel kernel convolution for entire pixels only with 256 steps of simple ana- log processing. Newly developed cyclic line access and row-parallel processing scheme in conjunction with the “only-nearest-neighbor in- terconnects” architecture has enabled a very simple implementation. A proof-of-concept chip was fabricated in a 0.35-(cid:0)m 2-poly 3-metal CMOS technology and the edge filtering at a rate of 200 frames/sec. has been experimentally demonstrated.

We developed a pneumatic conveyance system that consists of an array of micro air valves fabricated by MEMS technology. The array of 560 micro actuators successfully conveyed a small silicon chip, which was 3 mm/spl times/3 mm/spl times/100 /spl mu/m in size and 2 mg in weight. The chip was transferred to the force equilibrium point, which was generated by the arrayed actuators. In addition, we proposed a control method for the system; in this method, the equilibrium point is moved in order to transfer the object on it We also conveyed a small plastic chip, which was 5 mm /spl times/ 5 mm /spl times/ 1 mm in size and 38 mg in weight. In this case, efficient conveyance was achieved by detecting the object edge and applying tilted air jets to it. A full control of two-dimensional conveyance is under investigation. The control circuit chip was developed; the circuit is an array of cells that have optical sensors and processors. Distributed information processing by the cooperation of cells enabled detection of the shape of the conveyed object. Our future goal is to assemble the conveyance system with the circuit, and to realize the autonomous distributed micro conveyance system.