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Michal Roszkiewicz

dblp:34/4122 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Internet architecture and protocols · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Internet architecture and protocols › ATM networks
ATM switch architecture
0.011995
An Assigned-Buffer ATM Switching Architecture · INFOCOM 1995
Internet architecture and protocols
buffer management
0.011995
An Assigned-Buffer ATM Switching Architecture · INFOCOM 1995

Methods — techniques the papers use, named apart from their topics

simulation · 0.0
YearPublicationVenuePosition
1997 ORANGE - A New Class of ATM Switching Networks
abstract
Although the research on ATM elementary switches may be considered as close to the end, the problem of finding the optimum switching network still remains open. The main reason is that traditional switching networks (e.g., Clos switching networks) are not suitable for asynchronous environments, especially due to poor performance of last stages. Moreover, the load is not distributed equally over all switching elements inside networks of this class. In this paper a new type of switching network, referred to as polyhedral switching network is introduced. The key idea of a proposed solution is based on placing elementary switches on a sphere-shaped surface. Any set of adjacent switches forms a polygon, and the polygons, in turn, form a polyhedron. It is shown that such an arrangement is more convenient and suitable for ATM switching than switching networks known to date.
Andrzej Jajszczyk, Michal Roszkiewicz
ICC (1)2
1995 An Assigned-Buffer ATM Switching Architecture
abstract
There has been a great technological advancement in microelectronics and communications, which forces, among others, investigations on ATM switching architectures. Researchers keep on searching an efficient architecture, able to perform at a wide range of traffic loads and patterns, ensuring both minimum probability of cell loss as well as minimum cell delay. The authors propose one more architecture. The main goal is to create an architecture capable of operating at very high data rates. As the result, the switch uses the fastest method of buffer management, and is characterized by sufficiently low probability of blocking and short delay time. Appropriate simulation results are presented and some implementation issues are discussed.
Andrzej Jajszczyk, Michal Roszkiewicz
INFOCOM2