Road transport accounts for approximately 75% of emissions within the transportation sector, highlighting the need not only for cleaner vehicles but also for intelligent, connected infrastructure. Cyber-physical infrastructure (CPI) enables emerging technologies such as intelligent transport systems (ITS) and digital twins (DT), providing a foundation for enhanced planning, decision-making, and real-time optimisation. The effectiveness of DT-enabled ITS depends on reliable, low-latency communication networks like 5G and beyond, which face challenges such as beam blockage due to urban mobility and obstructions. To address this challenge, we propose a configurable simulation framework that models realistic urban scenarios, including connected autonomous vehicles (CAVs) dynamics, traffic congestion, and roadside units (RSUs) deployment strategies. Through three case studies, we examine the influence of traffic density, RSU height, and RSU count on beam blockage events and received signal strength (RSS). Our findings highlight key trade-offs: while taller RSUs reduce beam blockages, they incur greater propagation losses; likewise, denser RSU deployments improve connectivity up to a point, beyond which additional units result in marginal improvements. These insights provide practical guidance for designing resilient, low-latency communication infrastructures and highlight the need for intelligent, adaptive solutions to proactively mitigate blockage events in real time for sustainable and time-sensitive ITS applications.

With the exponential growth of data traffic, ensuring reliable and efficient network testing has become critical throughout design, implementation, and management operations. As testing is essential to ensure that changes in configuration or traffic conditions do not degrade user experience, current testing practices rely heavily on manual configuration and simulators. This reliance leads to time-consuming, difficult-to-scale, and expert-dependent processes. To address these limitations, our work explores the role of Automated Machine Learning (AutoML)–based automatically generated Digital Twin (DT) in network testing to enable rapid and scalable testing across diverse network conditions. By integrating this approach with a network service controller for configuration optimization, our results evidence an improvement that DT-enabled testing achieves high accuracy while being approximately 25,000 times faster than simulator-based testing. The implications of these findings, suggest that automated DT generation through AutoML can reduce dependence on manual modeling, allow DTs to adapt to diverse test scenarios, and enhance scalability for complex network.

In the past decade, Digital Twins (DTs) have emerged as a key enabler of industry digitalisation. As digital representations of physical objects and processes, DTs integrate a range of technologies to support applications from process monitoring to policymaking. However, increased system integration expands their attack surface, heightening cybersecurity risks. Efforts to integrate DTs into larger ecosystems have further intensified these concerns. Cybersecurity is inherently a socio-technical challenge influenced by various organisational and governance considerations. However, cybersecurity research on DTs has remained predominantly technical. As such, the current understanding of how organisational cybersecurity challenges emerge in DT contexts is limited. This work addresses this gap through a critical analysis of literature, examining how cybersecurity is conceptualised in DT implementation and the extent to which organisational cybersecurity challenges are addressed. Our analysis demonstrates that cybersecurity is widely acknowledged as a challenge in DT implementation. Nevertheless, most research offers limited in-depth analysis of specific cybersecurity challenges in real-world contexts. When addressed, cybersecurity was primarily framed around confidentiality and privacy, while other elements including data integrity and system availability are overlooked. Where cybersecurity has been the primary focus, works have been overwhelmingly technical, overlooking organisational complexities that affect cybersecurity in practice. This highlights a clear gap in understanding of how organisational cybersecurity challenges emerge in DTs. We conclude by outlining an agenda for future research to support more effective and secure approaches to DT implementation.

Leveraging limited data to synthesize an additional training set is essential for robotic vision, particularly in dynamic environments where collecting large datasets is impractical. Traditional robotic vision systems rely on extensive training data for object recognition and scene understanding but struggle to generalize to real-world variations, such as lighting conditions, occlusions, and sensor noise. This article proposes causal diffuse variational autoencoder (causal DiffuseVAE), a novel method integrating causal inference with high-fidelity image synthesis to generate counterfactual images. By combining the disentanglement properties of variational autoencoders (VAEs) with the generative capabilities of diffusion models, causal DiffuseVAE produces realistic, interpretable simulations of variations, such as shadows and occlusions. This combination enables data-efficient generative modeling by learning from small subsets and synthesizing missing or unseen samples. In addition, causal inference ensures that generated data follow real-world dependencies, making it robust and interpretable for deployment in unpredictable environments. Four baseline approaches are evaluated across six different datasets, demonstrating that causal DiffuseVAE consistently outperforms the four baseline approaches.

Autonomous vehicles (AVs) promise substantial gains in safety, reliability, and decarbonization, yet safe and efficient interaction in dynamic, heterogeneous traffic remains a key barrier to large-scale deployment. Deep reinforcement learning (DRL) has emerged as a data-driven approach for learning adaptive decision policies that handle complex, unpredictable environments better than rule-based methods. However, different scenarios impose distinct requirements, necessitating scenario-specific algorithms. This survey systematically reviews DRL for four typical scenarios (highways, on-ramp merging, roundabouts, and unsignalized intersections), summarizes road features and recent advances, and evaluates methods using five criteria: driving safety, driving efficiency, training efficiency, unselfishness, and interpretability (DDTUI). Each DDTUI criterion is analyzed with respect to the reviewed algorithms. In addition, a dedicated scenario-centric learning transferability analysis is introduced that systematically evaluates whether each reviewed method demonstrates scene-specific learning improvements and assesses how effectively their designs transfer across the four scenarios. Finally, the challenges for future DRL-based decision-making algorithms are summarized.

Humanity is reexamining how we co-create part-nerships with systems required to adapt to our changing needs. Robotic fleet autonomy in Inspection, Maintenance and Repair (IMR) demands robust operational governance, resilience in dynamic operating environments, and a diverse range of capabilities tailored to specific assets. This paper proposes a Symbiotic Multi-Robot Fleet (SMuRF) deployed in partnership with a human-in-the-Ioop via an operational decision support interface. Symbiosis provides a new collab-orative learning strategy to increase robot team performance and resilience to stochastic environmental variables while improving cyber-physical system management for a human-in-the-Ioop. The management of the SMuRF is implemented via a digital architecture that permits near to real-time communication for up to 1800 distributed robots, sensors, and assets. The measured productivity resulted in an improvement between 23 - 62 % due to optimized fleet management and task allocation within the SMuRF. The SMuRF has been validated via an autonomous mission evaluation scenario for an offshore substation with an induced fault on a robot, where autonomous symbiotic interactions utilizing machine learning rectify the issues to ensure the resilience of the mission for the multi-robot fleet.

Decarbonizing the residential sector is challenging due to the complexities in balancing energy consumption optimisation, occupant comfort, and health. Digitalization has emerged as a critical enabler to address these challenges, which could offer data-driven insights to realize this balance and achieve scalable impact, which many existing studies lack. This paper introduces an integrated Cyber-Physical and AI-driven methodology to digitalize Scottish Social housing and tackle these challenges. Our approach employs a low-power Long Range Wide Area Network (LoRaWAN) based internet of Things (IoT) architecture, combining smart plugs, clamp sensors, and environmental sensors to monitor CO2, temperature, humidity, energy usage at the appliance level, and other critical parameters. Predictive analytics on air quality and energy patterns are also enabled, delivering actionable insights for retrofitting and behavioral optimization. A case study conducted in a Scottish house demonstrated the ability of the proposed system to identify energy inefficiencies. Results show that the system effectively identified energy waste: an average of approximately 30-60% of energy being consumed during unoccupied periods, across multiple appliances. Furthermore, the system achieved over 95 % accuracy in predicting CO2indoor ppm, enabling relevant proactive actions to future unhealthy air quality conditions. Furthermore, data analytics on thermal fluctuations enabled the identification of poorly insulated rooms, providing insights for actionable retrofitting strategies. The findings highlight the system's ability to reduce energy waste, lower operational costs, and optimize retrofit investments, offering a scalable pathway to achieve low-carbon living standards.

The evolution of information and communication technologies has affected all fields of science, including health sciences. However, the rate of technological innovation adoption by the healthcare sector has been historically slow, compared to other industrial sectors. Innovation in computer modeling and simulation approaches has changed the landscape in biomedical applications and biomedicine, paving the way for their potential contribution in reducing, refining, and partially replacing animal and human clinical trials. In Silico Clinical Trials (ISCT) allow the development of virtual populations used in the safety and efficacy testing of new drugs and medical devices. This White Paper presents the current framework for ISCT, the role of in silico medicine research communities, the different perspectives (research, scientific, clinical, regulatory, standardization, data quality, legal and ethical), the barriers, challenges, and opportunities for ISCT adoption. In addition, an overview of successful ISCT projects, market-available platforms, and FDA- approved paradigms, along with their vision, mission and outcomes are presented.

Decision making at unsignalized intersections presents significant challenges for autonomous vehicles (AVs), particularly in mixed traffic scenarios where both AVs and human-driven vehicles (HDVs) must safely coordinate their movements. This paper proposes a safety-critical multi-agent Monte Carlo tree search (MCTS) framework that integrates deterministic and probabilistic predictions to enable cooperative decision making in complex intersection scenarios. The framework incorporates three main innovations: 1) a safety assessment mechanism that systematically handles AV-to-AV (V2V), AV-to-HDV (V2H), and Vehicle-to-Road (V2R) interactions using dynamic safety thresholds and spatiotemporal risk metrics, 2)an adaptive HDV behavior awareness by combining the Intelligent Driver Model (IDM) with probabilistic distributions, and 3)a multi-objective reward function optimization approach that balances safety, efficiency, and cooperation. Extensive simulations demonstrate our framework’s efficacy and superior capability in ensuring safe and efficient intersection navigation across the fully-autonomous scenario (100% AVs) and challenging mixed traffic scenario (50% AVs +50% HDVs). Compared to benchmarks, our method reduces trajectory deviations by up to 37.56% in the fully-autonomous scenario and 62.43% in the mixed traffic scenario, while maintaining significantly lower Post-Encroachment Time (PET) violations (0% and 2.8%, respectively).

Autonomous lane changing requires balancing safety, comfort, and efficiency while managing complex spatiotemporal vehicle interactions. Current methods often separate risk assessment from trajectory planning, leading to either conservative or unsafe maneuvers. This paper presents a contingency-aware spatiotemporal optimization framework that integrates dynamic risk assessment and trajectory optimization to ensure the autonomous host vehicle (HV) achieve safer, more efficient lane changes. First, the HV uses a dynamic risk field method to assess the collision risk with surrounding vehicles (SVs) in real-time, integrating dynamic obstacle interactions through modified Gaussian distributions. Second, a spatiotemporal safety corridor construction scheme leverages regression-based boundaries to transform spatiotemporal requirements into manageable optimization constraints. Third, the HV adopts a contingency-aware model predictive control framework that incorporates SVs uncertainty for human-like lane changes. The formulated optimization problem is solved using sequential quadratic programming with stability and recursive feasibility. Simulations confirm that our approach ensures safety and comfort of the HV across lane changing scenarios, achieving smoother trajectories, improved stability, and enhanced safety margins, with up to 95% reductions in longitudinal and lateral accelerations and a 27% decrease in lane-changing time.

Automated Vehicles (AVs) will coexist with Human-Driven Vehicles (HDVs) for a long time. AVs must navigate safely among HDVs while maintaining smooth traffic flow. To facilitate this, the decision making system of AVs must accurately assess HDV intentions while accounting for inherent uncertainties. Current HDV intention prediction models often misclassify these intentions, leading to unsafe navigation decisions. This study introduces a three-stage Bayesian sequential game-based decision making architecture designed for AV operation. In the first stage, the AV utilizes a temporal neural network to classify vehicle intentions. In the second stage, a sequential game is solved to determine optimal actions by predicting future HDV states. The final stage, serving as a validation stage, identifies and corrects misclassifications from the first stage by predicting HDV future positions, incorporating models that account for potential deviations from the ground truth. Simulation results indicate a 93.5±0.5% accuracy in initial intention predictions, facilitating swift and effective decision making. The validation stage further enhances safety by promptly correcting errors, ensuring reliable navigation for AVs in HDV environments.

Intelligent transportation systems are an emerging technology that facilitates real-time vehicle-to-everything communication. Hence, securing and authenticating data packets for intra- and inter-vehicle communication are fundamental security services in vehicular ad-hoc networks (VANETs). However, public-key cryptography (PKC) is commonly used in signature-based authentication, which consumes significant computation resources and communication bandwidth for signatures generation and verification, and key distribution. Therefore, physical layer-based secret key extraction has emerged as an effective candidate for key agreement, exploiting the randomness and reciprocity features of wireless channels. However, the imperfect channel reciprocity generates discrepancies in the extracted key, and existing reconciliation algorithms suffer from significant communication costs and security issues. In this paper, PKC-based authentication is used for initial legitimacy detection and exchanging authenticated probing packets. Accordingly, we propose a blockchain-based reconciliation technique that allows the trusted third party (TTP) to publish the correction sequence of the mismatched bits through a transaction using a smart contract. The smart contract functions enable the TTP to map the transaction address to vehicle-related information and allow vehicles to obtain the transaction contents securely. The obtained shared key is then used for symmetric key cryptography (SKC)-based authentication for subsequent transmissions, saving significant computation and communication costs. The correctness and security robustness of the scheme are proved using Burrows–Abadi–Needham (BAN)-logic and Automated Validation of Internet Security Protocols and Applications (AVISPA) simulator. We also discussed the scheme’s resistance to typical attacks. The scheme’s performance in terms of packet delay and loss ratio is evaluated using the network simulator (OMNeT++). Finally, the computation analysis shows that the scheme saves ∼99% of the time required to verify 1000 messages compared to existing PKC-based schemes.

The global effort to mitigate climate change has led to significant investments in both large-scale renewable energy and low carbon generation, as well as a significant increase in local, individual and community based smart local energy systems (SLES). SLES have the potential to support fast track decarbonization and support a more democratic and accessible route to energy services. However, there are significant techno-economic challenges to the viability of SLES. With respect to this challenge our paper focuses on the analyzing the role of individual prosumers and consumers in the energy market enabled through SLES. Prosumers can directly trade energy with each other via peer-to-peer (P2P) trading or as a community via peer-to-community (P2C) trading. We examine how SLES can support the optimization of benefits between prosumers and consumers in local communities and the implications this has on the wider electrical network. We design a P2C trading model in MATLAB for a community of 20 agents. Our framework and strategies are then applied across several simulation scenarios for a community of varying ratio of prosumers and consumers. From our findings, we can conclude that P2C trading, implemented with optimal battery management, benefitted the prosumers and consumers financially as well as reducing the congestion and demand on the wider electrical network. The findings from the simulation also suggests that there is an optimal ratio of prosumers to consumers, indicating that a community with prosumer-consumer ratio of 7:13 coupled with a community battery model, deliver optimal returns for the prosumers.

Given the pressing need for assuring algorithmic transparency, Explainable AI (XAI) has emerged as one of the key areas of AI research. In this paper, we develop a novel Bayesian extension to the LIME framework, one of the most widely used approaches in XAI – which we call BayLIME. Compared to LIME, BayLIME exploits prior knowledge and Bayesian reasoning to improve both the consistency in repeated explanations of a single prediction and the robustness to kernel settings. BayLIME also exhibits better explanation fidelity than the state-of-the-art (LIME, SHAP and GradCAM) by its ability to integrate prior knowledge from, e.g., a variety of other XAI techniques, as well as verification and validation (V&V) methods. We demonstrate the desirable properties of BayLIME through both theoretical analysis and extensive experiments.

Abstract Visual place recognition (VPR) is the process of recognising a previously visited place using visual information, often under varying appearance conditions and viewpoint changes and with computational constraints. VPR is related to the concepts of localisation, loop closure, image retrieval and is a critical component of many autonomous navigation systems ranging from autonomous vehicles to drones and computer vision systems. While the concept of place recognition has been around for many years, VPR research has grown rapidly as a field over the past decade due to improving camera hardware and its potential for deep learning-based techniques, and has become a widely studied topic in both the computer vision and robotics communities. This growth however has led to fragmentation and a lack of standardisation in the field, especially concerning performance evaluation. Moreover, the notion of viewpoint and illumination invariance of VPR techniques has largely been assessed qualitatively and hence ambiguously in the past. In this paper, we address these gaps through a new comprehensive open-source framework for assessing the performance of VPR techniques, dubbed “VPR-Bench”. VPR-Bench (Open-sourced at: https://github.com/MubarizZaffar/VPR-Bench ) introduces two much-needed capabilities for VPR researchers: firstly, it contains a benchmark of 12 fully-integrated datasets and 10 VPR techniques, and secondly, it integrates a comprehensive variation-quantified dataset for quantifying viewpoint and illumination invariance. We apply and analyse popular evaluation metrics for VPR from both the computer vision and robotics communities, and discuss how these different metrics complement and/or replace each other, depending upon the underlying applications and system requirements. Our analysis reveals that no universal SOTA VPR technique exists, since: (a) state-of-the-art (SOTA) performance is achieved by 8 out of the 10 techniques on at least one dataset, (b) SOTA technique in one community does not necessarily yield SOTA performance in the other given the differences in datasets and metrics. Furthermore, we identify key open challenges since: (c) all 10 techniques suffer greatly in perceptually-aliased and less-structured environments, (d) all techniques suffer from viewpoint variance where lateral change has less effect than 3D change, and (e) directional illumination change has more adverse effects on matching confidence than uniform illumination change. We also present detailed meta-analyses regarding the roles of varying ground-truths, platforms, application requirements and technique parameters. Finally, VPR-Bench provides a unified implementation to deploy these VPR techniques, metrics and datasets, and is extensible through templates.

Recent probabilistic model checking techniques can verify reliability and performance properties of software systems affected by parametric uncertainty. This involves modelling the system behaviour using interval Markov chains, i.e., Markov models with transition probabilities or rates specified as intervals. These intervals can be updated continually using Bayesian estimators with imprecise priors, enabling the verification of the system properties of interest at runtime. However, Bayesian estimators are slow to react to sudden changes in the actual value of the estimated parameters, yielding inaccurate intervals and leading to poor verification results after such changes. To address this limitation, we introduce an efficient interval change-point detection method, and we integrate it with a state-of-the-art Bayesian estimator with imprecise priors. Our experimental results show that the resulting end-to-end Bayesian approach to change-point detection and estimation of interval Markov chain parameters handles effectively a wide range of sudden changes in parameter values, and supports runtime probabilistic model checking under parametric uncertainty.

Demonstrating high reliability and safety for safety-critical systems (SCSs) remains a hard problem. Diverse evidence needs to be combined in a rigorous way: in particular, results of operational testing with other evidence from design and verification. Growing use of machine learning in SCSs, by precluding most established methods for gaining assurance, makes evidence from operational testing even more important for supporting safety and reliability claims. We revisit the problem of using operational testing to demonstrate high reliability. We use Autonomous Vehicles (AVs) as a current example. AVs are making their debut on public roads: methods for assessing whether an AV is safe enough are urgently needed. We demonstrate how to answer 5 questions that would arise in assessing an AV type, starting with those proposed by a highly-cited study. We apply new theorems extending our Conservative Bayesian Inference (CBI) approach, which exploit the rigour of Bayesian methods while reducing the risk of involuntary misuse associated (we argue) with now-common applications of Bayesian inference; we define additional conditions needed for applying these methods to AVs. Prior knowledge can bring substantial advantages if the AV design allows strong expectations of safety before road testing. We also show how naive attempts at conservative assessment may lead to over-optimism instead; why extrapolating the trend of disengagements (take-overs by human drivers) is not suitable for safety claims; use of knowledge that an AV has moved to a “less stressful” environment. While some reliability targets will remain too high to be practically verifiable, our CBI approach removes a major source of doubt: it allows use of prior knowledge without inducing dangerously optimistic biases. For certain ranges of required reliability and prior beliefs, CBI thus supports feasible, sound arguments. Useful conservative claims can be derived from limited prior knowledge.

Robots are increasingly used to carry out critical missions in extreme environments that are hazardous for humans. This requires a high degree of operational autonomy under uncertain conditions, and poses new challenges for assuring the robot’s safety and reliability. In this paper, we develop a framework for probabilistic model checking on a layered Markov model to verify the safety and reliability requirements of such robots, both at pre-mission stage and during runtime. Two novel estimators based on conservative Bayesian inference and imprecise probability model with sets of priors are introduced to learn the unknown transition parameters from operational data. We demonstrate our approach using data from a real-world deployment of unmanned underwater vehicles in extreme environments.

Energy audit in buildings is an essential task for optimal energy management and operations. This paper focuses on a machine learning pipeline to quantify heat loss using 60,000 thermal images in buildings. The images are captured from a small Unmanned Aerial System (sUAS) over the last two years to form a large thermal data repository. Intense efforts are made to annotate multiple sections of the buildings (e.g. windows, doors, ground, facade, trees, and sky). Data augmentation processes are then applied to generate a large comprehensive training data set. Object detection and instance segmentation models such as Mask R-CNN, Fast R-CNN, and Faster R-CNN were trained, and tested. The preliminary results indicate that Mask R-CNN has a larger mean average precision (mAP) of (83%) over R-CNN (51%), Fast R-CNN (62%), and Faster R-CNN (62 %) for a threshold of 50%. The surface temperature values from these thermal images (pixel-by-pixel) were then used in the standard heat transfer coefficient (U-value in BTU/hr/Sq.ft./F) calculations.

There is an urgent societal need to assess whether autonomous vehicles (AVs) are safe enough. From published quantitative safety and reliability assessments of AVs, we know that, given the goal of predicting very low rates of accidents, road testing alone requires infeasible numbers of miles to be driven. However, previous analyses do not consider any knowledge prior to road testing - knowledge which could bring substantial advantages if the AV design allows strong expectations of safety before road testing. We present the advantages of a new variant of Conservative Bayesian Inference (CBI), which uses prior knowledge while avoiding optimistic biases. We then study the trend of disengagements (take-overs by human drivers) by applying Software Reliability Growth Models (SRGMs) to data from Waymo's public road testing over 51 months, in view of the practice of software updates during this testing. Our approach is to not trust any specific SRGM, but to assess forecast accuracy and then improve forecasts. We show that, coupled with accuracy assessment and recalibration techniques, SRGMs could be a valuable test planning aid.

The geometry of a point cloud is commonly represented by an octree recursively decomposing a 3D volume into eight child sub-volumes. Said volumes and sub-volumes are associated with nodes and child-nodes of the octree. The geometry is defined by the occupancy information indicating the presence or not of a point in each of the sub-volumes. This naturally leads to an eight-bit occupancy information to be coded for each internal node of the tree.

In this paper the challenges of creating accurate, scalable and usable energy demand models are discussed, in the context of existing simulation and data driven energy demand models. Results from high resolution bottom-up data and simulation-based energy demand analysis from a community energy project are provided. A novel Hidden Markov Modelling and Generalised Pareto (HMM-GP) methodology for simulating synthetic electrical demand profiles is validated for residential buildings at a temporal resolution of five minutes. The corresponding dynamic thermal demands for the various building archetypes within the community are also modelled. This is achieved using automated externally driven IES-VE (building simulation) models for arrays of control profiles, and is also compared against in-situ thermal measurements.

In this paper we present a review into data driven prognostics and its relevance to resilience in energy systems. A data driven remaining useful life prediction for Li-ion batteries utilizing data analysis via a relevance vector machine (RVM) model is shown to be within 5% accuracy when applied to large lifecycle datasets. Results demonstrate that due to the agile nature of prognostic models and their accuracy, prognostics and health management methods will be vital to resilient and sustainable energy systems.

The Range Extensions (RExt) of the High Efficiency Video Coding (HEVC) standard have recently been approved by both ITU-T and ISO/IEC. This set of extensions targets video coding applications in areas including content acquisition, postproduction, contribution, distribution, archiving, medical imaging, still imaging, and screen content. In addition to the functionality of HEVC Version 1, RExt provide support for monochrome, 4:2:2, and 4:4:4 chroma sampling formats as well as increased sample bit depths beyond 10 bits per sample. This extended functionality includes new coding tools with a view to provide additional coding efficiency, greater flexibility, and throughput at high bit depths/rates. Improved lossless, near-lossless, and very high bit-rate coding is also a part of the RExt scope. This paper presents the technical aspects of HEVC RExt, including a discussion of RExt profiles, tools, applications, and provides experimental results for a performance comparison with previous relevant coding technology. When compared with the High 4:4:4 Predictive Profile of H.264/Advanced Video Coding (AVC), the corresponding HEVC 4:4:4 RExt profile provides up to ~25$ %, ~32%, and ~36% average bit-rate reduction at the same PSNR quality level for intra, random access, and low delay configurations, respectively.

In this paper, we show that the vulnerability of memory components due to data retention in the presence of soft errors exhibit orders of magnitude variations with applications through extensive analysis of MiBench benchmarks. Underpinning such analysis, we propose a novel application-specific design flow for joint energy efficiency and reliability optimization. The energy efficiency is achieved through voltage/frequency scaling (VFS), while reliability is achieved through suitably choosing the appropriate protection policies (L1-Cache resizing and selective ECC) for hierarchical memory components. Fundamental to such joint optimization is a design analysis framework, which can analyze trade-off between memory protection policies considering the impact of VFS, and apply design optimization algorithm to provide with an energy-efficient design, while meeting a given reliability target. Using this framework the proposed design flow is validated through extensive number of application case studies based on ARMv7 processors modeled in GEM5. We show that the joint consideration of cache resizing and VFS can improve the L1-Cache reliability by up to 5x compared to VFS alone, while incurring <10% energy overhead. Additionally, using selective ECC for L2-Cache and DRAM, we show that energy consumption can be reduced by up to 40%.

Navigation is instrumental in the successful deployment of Autonomous Underwater Vehicles (AUVs). Sensor hardware is installed on AUVs to support navigational accuracy. Sensors, however, may fail during deployment, thereby jeopardizing the mission. This work proposes a solution, based on an adaptive dynamic model, to accurately predict the navigation of the AUV. A hydrodynamic model, derived from simple laws of physics, is integrated with a powerful non-parametric regression method. The incremental regression method, namely the Locally Weighted Projection Regression (LWPR), is used to compensate for un-modeled dynamics, as well as for possible changes in the operating conditions of the vehicle. The augmented hydrodynamic model is used within an Extended Kalman Filter, to provide optimal estimations of the AUV's position and orientation. Experimental results demonstrate an overall improvement in the prediction of the vehicle's acceleration and velocity.

This paper presents a technique, called subclock power gating, for reducing leakage power during the active mode in low performance, energy-constrained applications. The proposed technique achieves power reduction through two mechanisms: 1) power gating the combinational logic within the clock period (subclock) and 2) reducing the virtual supply to less than Vth rather than shutting down completely as is the case in conventional power gating. To achieve this reduced voltage, a pair of nMOS and pMOS transistors are used at the head and foot of the power gated logic for symmetric virtual rail clamping of the power and ground supplies. The subclock power gating technique has been validated by incorporating it with an ARM Cortex-M0 microprocessor, which was fabricated in a 65-nm process. Two sets of experiments are done: the first experimentally validates the functionality of the proposed technique in the fabricated test chip and the second investigates the utility of the proposed technique in example applications. Measured results from the fabricated chip show 27% power saving during the active mode for an example wireless sensor node application when compared with the same microprocessor without subclock power gating.

Complex SoCs from servers to intelligent sensors are increasingly built up from heterogeneous IP cores and subsystems. Accelerator blocks or additional processor cores support both general purpose and graphics optimized processing in mobile SoCs, but the number of cores that may be simultaneously active is typically restricted for both battery life and thermal package limits. Power gating is the primary approach to cutting the leakage power for inactive blocks, while state retention and standby voltage scaling can be valuable enhancements for improving energy and latency costs for such leakage mitigation schemes. This paper describes work on techniques that look promising to build on current multi-voltage EDA tools and power intent, without the costs of resorting to full-custom design techniques.

To meet the still growing compression efficiency needs for high definition content, ITU and MPEG are now defining the High Efficiency Video Coding (HEVC) standard. The HEVC codec still relies on a hybrid motion compensated predictive video coding architecture as its H.264/AVC ancestor though novel coding tools are introduced. These novel coding tools provide a highly uncorrelated prediction residue for which classical frequency decomposition methods as the discrete cosine transform may not provide an effective energy compaction. Therefore this paper proposes a transform skip mode which allows skipping one or both directions where the transform is applied. The proposed transform skip mode is integrated in the HEVC codec and is able to provide bitrate reductions of up to 5% at the same objective quality when compared with the HEVC reference codec.

This session consists of three industry papers invited for their viewpoints on the challenges on future needs for low-power electronic design from an industry perspective. The authors are experts on the field of low-power design techniques as well as in CAD tools for implementing these techniques, both areas that are critical to actually achieving the goals of aggressive chip design. In addition, the authors provide a perspective of the lessons learned and the evolution of the techniques that have enabled mobile platforms to become so widely deployed and a big part of our everyday lives.

In this paper the lessons learned as an IP provider addressing the transfer of low power designs and implementation flows and methodologies into energy-efficient System-on-Chip products are discussed, followed by a preview of the more promising techniques for future deployment.

Advances in video compression technology have been driven by ever-increasing processing power available in software and hardware. The emerging High Efficiency Video Coding (HEVC) standard aims to provide a doubling in coding efficiency with respect to the H.264/AVC high profile, delivering the same video quality at half the bit rate. In this paper, complexity-related aspects that were considered in the standardization process are described. Furthermore, profiling of reference software and optimized software gives an indication of where HEVC may be more complex than its predecessors and where it may be simpler. Overall, the complexity of HEVC decoders does not appear to be significantly different from that of H.264/AVC decoders; this makes HEVC decoding in software very practical on current hardware. HEVC encoders are expected to be several times more complex than H.264/AVC encoders and will be a subject of research in years to come.

This paper discusses one of the key challenges of design-for-yield: namely, the difficulty in correlating observed behavior with modeled behavior. In order to achieve good parametric yield, the design process must account for a large number of sources of variability in the silicon, ranging from those inherent in the device and wire models themselves through approximations made in library modeling, extraction, tool algorithms and so on. The problem is further complicated by defects and systematic errors that can be present in early silicon but are expected to be fixed as part of the volume ramp. In addition, environmental factors such as temperature and power delivery must be understood, and variation in the measurement equipment must also be correctly accounted for. Examples are given for validating standard cell and memory based designs as well as a general methodology that can be used to enable chip bring-up.

This paper presents a new technique, called sub-clock power gating, for reducing leakage power in digital circuits. The proposed technique works concurrently with voltage and frequency scaling and power reduction is achieved by power gating within the clock cycle during active mode unlike traditional power gating which is applied during idle mode. The proposed technique can be implemented using standard EDA tools with simple modifications to the standard power gating design flow. Using a 90nm technology library, the technique is validated using two case studies: 16-bit parallel multiplier and ARM Cortex-M0™ microprocessor, provided by our industrial project partner. Compared to designs without sub-clock power gating, in a given power budget, we show that leakage power saved allows 45× and 2.5× improvements in energy efficiency in the case of multiplier and microprocessor, respectively.

Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge this is the first study that analyzes recently proposed DFT solutions for testing power switches through SPICE simulations on a number of ISCAS benchmarks and presents the following contributions. It provides evidence of long discharge time when power switches are turned-off, when testing power switches using available DFT solutions. This may either lead to false test (false-fail or false-pass) or long test time. This problem is addressed through a simple and effective DFT solution to reduce the discharge time. The proposed DFT solution has been validated through SPICE simulation and shows an improvement in discharge time of at least 28-times, based on a number of ISCAS benchmarks synthesized with a 90-nm gate library.

Over the last twenty years the interfaces for accessing persistent storage within a computer system have remained essentially unchanged. Simply put, seek, read and write have defined the fundamental operations that can be performed against storage devices. These three interfaces have endured because the devices within storage subsystems have not fundamentally changed since the invention of magnetic disks. Non-volatile (flash) memory (NVM) has recently become a viable enterprise grade storage medium. Initial implementations of NVM storage devices have chosen to export these same disk-based seek/read/write interfaces because they provide compatibility for legacy applications. We propose there is a new class of higher order storage primitives beyond simple block I/O that high performance solid state storage should support. One such primitive, atomic-write, batches multiple I/O operations into a single logical group that will be persisted as a whole or rolled back upon failure. By moving write-atomicity down the stack into the storage device, it is possible to significantly reduce the amount of work required at the application, filesystem, or operating system layers to guarantee the consistency and integrity of data. In this work we provide a proof of concept implementation of atomic-write on a modern solid state device that leverages the underlying log-based flash translation layer (FTL). We present an example of how database management systems can benefit from atomic-write by modifying the MySQL InnoDB transactional storage engine. Using this new atomic-write primitive we are able to increase system throughput by 33%, improve the 90th percentile transaction response time by 20%, and reduce the volume of data written from MySQL to the storage subsystem by as much as 43% on industry standard benchmarks, while maintaining ACID transaction semantics.

Advanced intra prediction is one of the key components in highly efficient video coding since it reduces the bit-rate of the most costly intra frames. Combined Intra Prediction (CIP) is a novel tool that takes into account well established directional prediction from neighboring blocks, as well as local mean prediction from current block. In this way, it reduces bit-rate by further exploiting spatial redundancy. This paper proposes an implementation that will overcome its potential limitation limited parallelization capabilities. In order to make it more computationally parallelizable, adaptive open-loop prediction templates have been designed. Experiments have been performed which show that the proposed design preserves coding gains introduced by CIP, while providing a solution for more parallelizable, and therefore faster, implementations.

State retention power gating and voltage-scaled state retention are two effective design techniques, commonly employed in embedded processors, for reducing idle circuit leakage power. This paper presents a methodology for improving the reliability of embedded processors in the presence of power supply noise and soft errors. A key feature of the method is low cost, which is achieved through reuse of the scan chain for state monitoring, and it is effective because it can correct single and multiple bit errors through hardware and software, respectively. To validate the methodology, ARM® Cortex™-M0 embedded microprocessor (provided by our industrial project partner) is implemented in field-programmable gate array and further synthesized using 65-nm technology to quantify the cost in terms of area, latency, and energy. It is shown that the proposed methodology has a small area overhead (8.6%) with less than 4% worst-case increase in critical path and is capable of detecting and correcting both single bit and multibit errors for a wide range of fault rates.

Power gating is an effective technique for reducing leakage power which involves powering off idle circuits through power switches, but those power-gated circuits which need to retain their states store their data in state retention registers. When power-gated circuits are switched from sleep to active mode, sudden rush of current has the potential of corrupting the stored data in the state retention registers which could be a reliability problem. This paper presents a methodology for improving the reliability of power-gated designs by protecting the integrity of state retention registers through state monitoring and correction. This is achieved by scan chain data encoding and decoding. The methodology is compatible with EDA tools design and power gating control flows. A detailed analysis of the proposed methodology's capability in detecting and correcting errors is given including the area overhead and energy consumption of the protection circuitry. The methodology is validate using FPGA and show that it is possible to correct all single errors with Hamming code and detect all multiple errors with CRC-16 code. To the best of our knowledge this is the first study in the area of reliable power gating designs through state monitoring and correction.

We present the design, implementation, and evaluation of Direct File System (DFS) for virtualized flash storage. Instead of using traditional layers of abstraction, our layers of abstraction are designed for directly accessing flash memory devices. DFS has two main novel features. First, it lays out its files directly in a very large virtual storage address space provided by FusionIO's virtual flash storage layer. Second, it leverages the virtual flash storage layer to perform block allocations and atomic updates. As a result, DFS performs better and is much simpler than a traditional Unix file system with similar functionalities. Our microbenchmark results show that DFS can deliver 94,000 I/O operations per second (IOPS) for direct reads and 71,000 IOPS for direct writes with the virtualized flash storage layer on FusionIO's ioDrive. For direct access performance, DFS is consistently better than ext3 on the same platform, sometimes by 20%. For buffered access performance, DFS is also consistently better than ext3, and sometimes by over 149%. Our application benchmarks show that DFS outperforms ext3 by 7% to 250% while requiring less CPU power.

Addressing both standby and active power is a major challenge in developing system-on-chip designs for battery-powered products. Powering off sections of logic or memories loses internal register and RAM states so designers have to weigh up the benefits and costs of implementing state retention on some or all of the power gated subsystems where state recovery has significant real-time or energy cost, compared to resetting the subsystem and re-acquiring state from scratch. Library IP and EDA tools can support state retention in hardware synthesized from standard RTL, but due to the silicon area costs there is strong interest in only retaining certain selective state for example the ldquoarchitectural staterdquo of a CPU to implement sleep modes. Currently there is no known rigourous technique for checking the integrity of selective state retention, and this is due to the complexity of checking that the correctness of the design is not compromised in any way. The complexity is exacerbated due to the interaction between the retained and the non-retained state, and exhaustive simulation rapidly becomes infeasible. This paper presents a case study based on symbolic simulation for assisting the designers to design and implement selective retention correctly. The main finding of our study is that the programmer visible state or the architectural state of the CPU needs to be implemented using retention registers whilst other micro-architectural enhancements such as pipeline registers, TLBs and caches can be implemented using normal registers without retention. This has a profound impact on power and area savings for chip design. By selectively retaining the state of the programmer's ldquoarchitecturalrdquo model and not the increasing proportion of extra state, one can incorporate energy-efficient sleep modes. To the best of our knowledge this is the first study in the area of rigourous design and implementation of selective state retention.

One of today's most successful embedded devices, the mobile phone, embodies a set of challenging design requirements: long battery life, small size, high performance and low cost. The single parameter that complicates the simultaneous fulfilment of all of these design goals is energy efficiency of the system, since batteries only hold a finite amount of charge. To operate within the allotted energy budget, systems must be optimized for energy consumption during design and also at run-time. Increasingly it is not sufficient to statically optimize for worst-case conditions but designers must enable systems to adapt to conditions at run-time. The intelligent energy manager/spl trade/ (IEM) technology provides an integrated solution for addressing energy management of SoC devices. In this paper we present data about the energy consumption characteristics of a multiple power-domain based SoC which includes PDA functionality built around an ARM926EJ-S core.