Demo Data from EDBT 2026 / reviewers in the wild / expert
Richard Plasun
dblp:34/4775
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1998
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 91% Integrated circuit design · 9% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › technology computer-aided design
process and device simulation |
0.0 | 1 | 1998 | Integrated optimization capabilities in the VISTA technology CAD framework · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998 |
Electronic design automation
technology computer-aided design |
0.0 | 1 | 1998 | Integrated optimization capabilities in the VISTA technology CAD framework · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998 |
Integrated circuit design
semiconductor device characterization |
0.0 | 1 | 1998 | Integrated optimization capabilities in the VISTA technology CAD framework · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998 |
Methods — techniques the papers use, named apart from their topics
response surface methodology · 0.0optimization · 0.0design of experiments · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1998 | Integrated optimization capabilities in the VISTA technology CAD frameworkabstractAdvanced analysis features implemented in the Vienna Integrated System for TCAD Applications simulation environment are presented. These functionalities support automatic experiment generation (design of experiments), model fitting (response surface methodology), optimization, and calibration. They interact with the core modules of the framework supporting the simulation of the manufacturing process and electrical characterization of semiconductor devices. Two examples demonstrate the efficiency of these framework capabilities. The first one shows the optimization of the electrical characteristics of vertical double-diffused metal-oxide-semiconductor (MOS) field-effect transistors. The second example deals with the optimization of analytical doping profiles of MOS transistors. Richard Plasun, Michael Stockinger, Siegfried Selberherr |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |