Quality of service and network controllability are issues that have yet to be clearly defined for broadband packet switching networks. One method of influencing the quality of service and the controllability of packet switched networks is queue scheduling. Unfortunately, defining an optimal queue scheduling method is highly dependent upon the cost function chosen for a particular switch implementation. Therefore, the authors propose a VLSI generic queue scheduler that can emulate a wide variety of queue scheduling methods. They implement the VLSI generic queue scheduler using a VLSI system synthesis tool, OASIS, and through measurements explore the size and speed of various system configurations. The process of employing some scheduling methods in this architecture is also detailed.>

A pipelined common buffer architecture (PCBA) is proposed for memory based switching systems. Unlike previously proposed shared-memory switching system, the PCBA is suitable for prioritized and multicast (without multiple memory write) traffic for both fixed length and variable length cell/packet. Therefore, switching among ATM traffic and existing LAN can be accomplished. The PCBA can route both fixed-sized cell data and variable-sized packet data. It separates switching system control and packet/cell data streams (the dichotomy) inside the switching system to simplify the design process for identifying VLSI chips implementation. The PCBA also uses pipelining for both system control and data movement, to achieve the highest possible system throughput, i.e. one system buffer per system clock cycle. A system buffer in PCBA has fixed size N/spl times/W bits where N is the number of switch ports and W is the width of data path (number of bits transmitted/received to/from system buffer at one clock cycle by a switch port). Furthermore, the usage of external memory modules for both data and control memory takes full advantage of advances in commercial RAM technology. It can be seen that the PCBA not only can easily expand its queue size for different networking environments, but can also support future traffic types without modification to the architecture.>