Abstract We introduce , a new procedure that employs the quantified symmetric minimization algorithm from [12] to systematically derive quantified formulas that precisely capture the onset of cutoff and saturation in distributed protocols. performs symmetry-aware forward reachability to enumerate the reachable states of a finite protocol instance, and applies symmetry-preserving logic minimization to express these states as a minimum-cost finitely-quantified reachability formula. repeats this finite analysis process to derive a sequence of reachability formulas $$R_1, R_2, R_3, \cdots $$ R 1 , R 2 , R 3 , ⋯ at increasing protocol sizes. This process terminates at size k when $$R_k$$ R k is a unique solution to symmetric minimization that yields the exact set of reachable states when evaluated at size $$k+1$$ k + 1 . We define $$c:=k$$ c : = k as the cutoff size and $$R_c:=R_k$$ R c : = R k as the cutoff formula . Empirically, $$R_c$$ R c is shown to be a reachability invariant that encodes the reachable states for any protocol size. extends the finite analysis process in [12] by introducing two algorithmic enhancements: a depth-first search algorithm that enumerates the reachable states of a finite protocol by searching only for their symmetric quotient, and an extended quantification pattern inference algorithm that expresses explicit clause orbits of finite instances by logically equivalent quantified formulas. Empirical results demonstrate that, compared to the techniques used in [12], is able to analyze a larger corpus of protocols, derive more compact quantified inductive invariants, and converge at smaller cutoffs. In contrast to previous scholarship, offers a new angle for understanding the notions of cutoff and saturation of distributed protocols. In particular, it raises intriguing questions about the unexpected role of symmetric logic minimization in this much-researched area and opens new directions for further research.

Lamport's celebrated Paxos consensus protocol is generally viewed as a complex hard-to-understand algorithm. Notwithstanding its complexity, in this paper, we take a step towards automatically proving the safety of Paxos by taking advantage of three structural features in its specification: spatial regularity in its unordered domains, temporal regularity in its totally-ordered domain, and its hierarchical composition. By carefully integrating these structural features in IC3PO, a novel model checking algorithm, we were able to infer an inductive invariant that identically matches the human-written one previously derived with significant manual effort using interactive theorem proving. While various attempts have been made to verify different versions of Paxos, to the best of our knowledge, this is the first demonstration of an automatically-inferred inductive invariant for Lamport's original Paxos specification. We note that these structural features are not specific to Paxos and that IC3PO can serve as an automatic general-purpose protocol verification tool.

Whether representing strings, heap objects, or numerical vectors, arrays are pervasive in software. Unfortunately, while several software model checkers support arrays, they tend to struggle with many array-manipulating programs due to work expended generating theory lemmas that are ultimately irrelevant or redundant. By judicious abstraction of array operations to the logic of equality with uninterpreted functions (EUF), we show that we can directly reason about array reads and adaptively learn lemmas about array writes leading to significant performance improvements over existing approaches. We find that our model checker solves more than 100 more SV-COMP benchmarks than SPACER, a leading model checker.

We present AVR, a push-button model checker for verifying state transition systems directly at the source-code level. AVR uses information embedded in the word-level syntax of the design representation to automatically perform scalable model checking by combining a novel syntax-guided abstraction-refinement technique with a word-level implementation of the IC3 algorithm. AVR provides independently-verifiable certificates that offer provable assurance and are easy to relate to the word-level system. Moreover, proof certificates can be further used in innovative ways to extract key design information and are useful in a growing number of applications.

IC3-based algorithms have emerged as effective scalable approaches for hardware model checking. In this paper we evaluate six implementations of IC3-based model checkers on a diverse set of publicly-available and proprietary industrial Verilog RTL designs. Four of the six verifiers we examined operate at the bit level and two employ abstraction to take advantage of word-level RTL semantics. Overall, the word-level verifier employing data abstraction outperformed the others, especially on the large industrial designs. The analysis helped us identify several key insights on the techniques underlying these tools, their strengths and weaknesses, differences and commonalities, and opportunities for improvement.

Distributed systems are notoriously difficult to design and implement correctly. Formal verification provides correctness proofs, and has recently been successfully applied to various distributed systems. At the heart of a typical formal verification is a computer-checked proof with an inductive invariant. Finding this inductive invariant is the hardest part of the proof: a part that is currently undertaken manually by the developer and is responsible for most of the effort associated with formal verification.

Designing and implementing distributed systems correctly is a very challenging task. Recently, formal verification has been successfully used to prove the correctness of distributed systems. At the heart of formal verification lies a computer-checked proof with an inductive invariant. Finding this inductive invariant, however, is the most difficult part of the proof. Alas, current proof techniques require inductive invariants to be found manually---and painstakingly---by the developer.

Combinatorial objects in EDA applications exhibit a great amount of complexity and typically defy polynomial-time algorithms. To achieve acceptable performance, EDA tools seek to exploit various structures found in these objects in practice. In this work, we explore symmetries of Boolean functions and develop a new algorithm based on nested partition refinement, abstract group theory and Boolean satisfiability. We apply our algorithm to solve large-scale Boolean matching.

We adapt techniques from the constraint programming and satisfiability literatures to expedite the search for graph automorphisms. Specifically, we implement conflict-driven backjumping, several branching heuristics, andrestarts. To support backjumping, we extend high-performance search for graph automorphisms with a novel framework for conflict analysis. Empirically, these techniques improve performance up to several orders of magnitude.

It has long been recognized that it can be tedious and even infeasible for system administrators to figure out critical security problems residing in full attack graphs, even for small-sized enterprise networks. Therefore a trade-off between analysis accuracy and efficiency needs to be made to achieve a reasonable balance between completeness of the attack graph and its usefulness. In this paper, we provide an approach to attack graph distillation, so that the user can control the amount of information presented by sifting out the most critical portion of the full attack graph. The user can choose to see only the k most critical attack paths, based on specified severity metrics, e.g. the likelihood for an attacker to carry out certain exploit on certain machine and the chance of success. We transform an dependency attack graph into a Boolean formula and assign cost metrics to attack variables in the formula, based on the severity metrics. We then apply Minimum-Cost SAT Solving (MCSS) to find the most critical path in terms of the least cost incurred for the attacker to deploy multi-step attacks leading to certain crucial assets in the network. An iterative process inspired by Counter Example Guided Abstraction and Refinement (CEGAR) is designed to efficiently guide the MCSS to render solutions that contain a controlled number of realistic attack paths, forming a critical attack graph surface. Our method can distill critical attack graph surfaces from the full attack graphs generated for moderate-sized enterprise networks in only several minutes. Experiments on various sized network scenarios show that even for a small-sized critical attack graph surface (around 15% the size of the original full attack graph), the calculated risk metrics are good approximation of the values computed with the full attack graph, meaning the distilled critical attack graph surface is able to capture the crucial security problems in an enterprise network for further in-depth analysis.

In this paper, we report our findings on the impact of providing users with varying degrees of control in an automated interactive scheduling system. While automated scheduling techniques such as constraint optimization have been widely adopted in a variety of scheduling applications, such applications require that users relinquish a certain amount of control to the system. The implications of such a shift in control are not clear for people who oversee the scheduling of human activities, for example, case managers scheduling patient appointments in hospitals and clinics. We asked our participants to use a working prototype system for clinic scheduling to complete a series of scheduling problems that we designed. We varied the size of the problems---i.e., the number of patients to be scheduled---and the style of interaction in ways that are associated with different degrees of user control. We recorded standard usability metrics and conducted post-task written surveys and interviews. Our results suggest that although maintaining full user control decreases efficiency as the problem becomes larger, the participants still preferred to have full user control in completing scheduling tasks. We end with design implications in supporting users' increased acceptance of automated scheduling systems.

Many computational tools have recently begun to benefit from the use of the symmetry inherent in the tasks they solve, and use general-purpose graph symmetry tools to uncover this symmetry. However, existing tools suffer quadratic runtime in the number of symmetries explicitly returned and are of limited use on very large, sparse, symmetric graphs. This paper introduces a new symmetry-discovery algorithm which exploits the sparsity present not only in the input but also the output, i.e., the symmetries themselves. By avoiding quadratic runtime on large graphs, it improves state-of- the-art runtimes from several days to less than a second.

In today's SoC design cycles, debugging is one of the most time consuming manual tasks. CAD solutions strive to reduce the inefficiency of debugging by identifying error sources in designs automatically. Unfortunately, the capacity and performance of such automated techniques must be considerably extended for industrial applicability. This work aims to improve the performance of current state-of-the-art debugging techniques, thus making them more practical. More specifically, this work proposes a novel design debugging formulation based on maximum satisfiability (max-sat) and approximate max-sat. The developed technique can quickly discard many potential error sources in designs, thus drastically reducing the size of the problem passed to an existing debugger. The max-sat formulation is used as a pre-processing step to construct a highly optimized debugging framework. Empirical results demonstrate the effectiveness of the proposed framework as run-time improvements of orders of magnitude are consistently realized over a state-of-the-art debugger.

Optimized solvers for the Boolean satisfiability (SAT) problem have many applications in areas such as hardware and software verification, FPGA routing, planning, and so forth. Further uses are complicated by the need to express "counting constraints" in conjunctive normal form (CNF). Expressing such constraints by pure CNF leads to more complex SAT instances. Alternatively, those constraints can be handled by integer linear programming (ILP), but generic ILP solvers may ignore the Boolean nature of 0-1 variables. Therefore, specialized 0-1 ILP solvers extend SAT solvers to handle these so-called "pseudo-Boolean" (PB) constraints. This work provides an update on the on-going competition between generic ILP techniques and specialized 0-1 ILP techniques. To make a fair comparison, we generalize recent ideas for fast SAT-solving to more general 0-1 ILP problems that may include counting constraints and optimization. This generalization is embodied in our PB constraint solver and optimizer PBS, which is compared with state-of-the-art CNF and generic ILP solvers. Another aspect of our comparison is the evaluation on 0-1 ILP benchmarks that originate in electronic design automation (EDA) but that cannot be directly solved by an SAT solver. Specifically, we solve instances of the max-SAT and max-ONEs optimization problems, which seek to maximize the number of satisfied clauses and the "true" values over all satisfying assignments, respectively. Those problems have straightforward applications to SAT-based routing and are additionally important due to reductions from max-cut, max-clique, and min vertex cover. Our experimental results show that specialized 0-1 techniques implemented in PBS tend to outperform generic ILP techniques on Boolean optimization problems, as well as on general EDA SAT problems.

In this paper, we explore the application of counter-example-guided abstraction refinement (CEGAR) in the context of microprocessor correspondence checking. The approach utilizes automatic datapath abstraction augmented with automatic refinement based on 1) localization, 2) generalization, and 3) minimal unsatisfiable subset (MUS) extraction. We introduce several refinement strategies and empirically evaluate their effectiveness on a set of microprocessor benchmarks. The data suggest that localization, generalization, and MUS extraction from both the abstract and concrete models are essential for effective verification. Additionally, refinement tends to converge faster when multiple MUses are extracted in each iteration.

In this paper we describe our solver for systems of linear integer arithmetic logic. Such systems are commonly used in design verification applications and are classified under satisfiability modulo theories (SMT) problems. Recognizing the fact that in many such applications the majority of atoms are equalities or integer unit-two-variable inequalities (UTVPIs), we present a framework that integrates specialized theory solvers for those atoms within a SAT solver. The unique feature of our strategy is its simultaneous adoption of both a congruence-closure equality solver and a transitive-closure UTVPI solver to find a satisfiable set of those atoms. A full-scale ILP solver is then utilized to check the consistency of all integer constraints within the solution. Other notable features of our solver include its combined deduction and learning schemes that collectively make our solver distinct among similar solvers

We describe a SAT-based decision method for the underlying logic in many formal verification problems; i.e. the counter arithmetic logic with lambda expressions and uninterpreted functions (CLU). This logic is well suited for equivalence checking of two versions of a hardware design or the input and output of a compiler and has been recently utilized in several model checkers. Our method follows the general Satisfiability Modulo Theories or SMT(T) framework and combines a DPLL-style SAT solver with two theory solvers; one specific to equality and the other to separation inequality atoms within CLU. By adopting a combined implication scheme, we coordinate the efforts among theory solvers, and by efficiently processing uninterpreted functions involved in conflicts, we considerably improve the effectiveness of SAT learning and backtracking routines. Finally, we empirically demonstrate the effectiveness of our SMT(CLU) procedure and compare its performance to recent solvers on a wide range of hardware verification benchmarks.

Code optimization and high level synthesis can be posed as constraint satisfaction and optimization problems, such as graph coloring used in register allocation. Graph coloring is also used to model more traditional CSPs relevant to AI, such as planning, time-tabling and scheduling. Provably optimal solutions may be desirable for commercial and defense applications. Additionally, for applications such as register allocation and code optimization, naturally-occurring instances of graph coloring are often small and can be solved optimally. A recent wave of improvements in algorithms for Boolean satisfiability (SAT) and 0-1 Integer Linear Programming (ILP) suggests generic problem-reduction methods, rather than problem-specific heuristics, because (1) heuristics may be upset by new constraints, (2) heuristics tend to ignore structure, and (3) many relevant problems are provably inapproximable. Problem reductions often lead to highly symmetric SAT instances, and symmetries are known to slow down SAT solvers. In this work, we compare several avenues for symmetry breaking, in particular when certain kinds of symmetry are present in all generated instances. Our focus on reducing CSPs to SAT allows us to leverage recent dramatic improvement in SAT solvers and automatically benefit from future progress. We can use a variety of black-box SAT solvers without modifying their source code because our symmetry-breaking techniques are static, i.e., we detect symmetries and add symmetry breaking predicates (SBPs) during pre-processing. An important result of our work is that among the types of instance-independent SBPs we studied and their combinations, the simplest and least complete constructions are the most effective. Our experiments also clearly indicate that instance-independent symmetries should mostly be processed together with instance-specific symmetries rather than at the specification level, contrary to what has been suggested in the literature.

Identifying and breaking the symmetries of conjunctive normal form (CNF) formulae has been shown to lead to significant reductions in search times. Symmetries in the search space are broken by adding appropriate symmetry-breaking predicates (SBPs) to an SAT instance in CNF. The SBPs prune the search space by acting as a filter that confines the search to nonsymmetric regions of the space without affecting the satisfiability of the CNF formula. For symmetry breaking to be effective in practice, the computational overhead of generating and manipulating SBPs must be significantly less than the runtime savings they yield due to search space pruning. In this paper, we describe a more systematic and efficient construction of SBPs. In particular, we use the cycle structure of symmetry generators, which typically involve very few variables, to drastically reduce the size of SBPs. Furthermore, our new SBP construction grows linearly with the number of relevant variables as opposed to the previous quadratic constructions. Our empirical data suggest that these improvements reduce search runtimes by one to two orders of magnitude on a wide variety of benchmarks with symmetries.

With impressive progress in Boolean Satisfiability (SAT) solving and several extensions to pseudo-Boolean (PB) constraints, many applications that use SAT, such as high-performance formal verification techniques are still restricted to checking satisfiability of certain conditions. However, there is also frequently a need to express a preference for certain solutions. Extending SAT-solving to Boolean optimization allows the use of objective functions to describe a desirable solution. Although recent work in 0-1 Integer Linear Programming (ILP) offers extensions that can optimize a linear objective function, this is often achieved by solving a series of SAT or ILP decision problems. Our work articulates some pitfalls of this approach. An objective function may complicate the use of any symmetry that might be present in the given constraints, even when the constraints are unsatisfiable and the objective function is irrelevant. We propose several new techniques that treat objective functions differently from CNF/PB constraints and accelerate Boolean optimization in many practical cases. We also develop an adaptive flow that analyzes a given Boolean optimization problem and picks the symmetry-breaking technique that is best suited to the problem characteristics. Empirically, we show that for non-trivial objective functions that destroy constraint symmetries, the benefit of static symmetry-breaking is lost but dynamic symmetry-breaking accelerates problem-solving in many cases. We also introduce a new objective function, Localized Bit Selection (LBS), that can be used to specify a preference for bit values in formal verification applications.

The paper introduces a new SAT (satisfiability) solver that integrates logic-based reasoning and integer programming methods to systems of CNF and PB constraints. Its novel features include an efficient PB literal watching strategy and several PB learning methods that take advantage of the pruning power of PB constraints while minimizing their overhead.

Abstraction plays a critical role in verifying complex sys-tems. A number of languages have been proposed to model hardware systems by, primarily, abstracting away their wide datapaths while keeping the low-level details of their control logic. This leads to a significant reduction in the size of the state space and makes it possible to verify intricate control interactions formally. These languages, however, require that the abstraction be done manually, a tedious and error-prone process. In this paper we describe Vapor, a tool that auto-matically abstracts behavioral RTL Verilog to the CLU lan-guage used by the UCLID system. Vapor performs a sound abstraction with emphasis on minimizing false errors. Our method is fast, systematic, and complements UCLID by serving as a back-end for dealing with UCLID counterexamples. Preliminary results show the feasibility of automatic abstraction and its utility in formal verification.

Instances of the Boolean satisfiability problem (SAT) arise in many areas of circuit design and verification. These instances are typically constructed from some human-designed artifact, and thus are likely to possess much inherent symmetry and sparsity. Previous work[4] has shown that exploiting symmetries results in vastly reduced SAT solver run times, often with the search for the symmetries themselves dominating the total SAT solving time. Our contribution is twofold. First, we dissect the algorithms behind the venerable NAUTY[9] package, particularly the partition refinement procedure responsible for the majority of search space pruning as well as the majority of run time overhead. Second, we present a new symmetry-detection tool, SAUCY, which outperforms NAUTY by several orders of magnitude on the large, structured CNF formulas generated from typical EDA problems.

This paper describes a new algorithm for extracting unsatisfiable subformulas from a given unsatisfiable CNF formula. Such unsatisfiable cores can be very helpful in diagnosing the causes of infeasibility in large systems. Our algorithm is unique in that it adapts the learning process of a modern SAT solver to identify unsatisfiable subformulas rather than search for satisfying assignments. Compared to existing approaches, this method can be viewed as a bottom-up core extraction procedure which can be very competitive when the core sizes are much smaller than the original formula size. Repeated runs of the algorithm with different branching orders yield different cores. We present experimental results on a suite of large automotive benchmarks showing the performance of the algorithm and highlighting its ability to locate not just one but several cores.

Code optimization and high level synthesis can be posed as constraint satisfaction and optimization problems, such as graph coloring used in register allocation. Naturally-occurring instances of such problems are often small and can be solved optimally. A recent wave of improvements in algorithms for Boolean satisfiability (SAT) and 0-1 ILP suggests generic problem-reduction methods, rather than problem-specific heuristics, because: (1) heuristics are easily upset by new constraints; (2) heuristics tend to ignore structure; and (3) many relevant problems are provably inapproximable. The NP-spec project offers a language to specify NP-problems and automatic reductions to SAT. Problem reductions often lead to highly symmetric SAT instances, and symmetries are known to slow down SAT solvers. In this work, we compare several avenues for symmetry-breaking, in particular when certain kinds of symmetry are present in all generated instances. Our surprising conclusion is that instance-independent symmetries should often be processed together with instance-specific symmetries rather than earlier, at the specification level.

We present empirical analyses of two Boolean satisfiability (SAT) formulations of FPGA (field programmable gate array) detailed routing constraints. Boolean SAT-based routing transforms a routing problem into a Boolean SAT instance by rendering geometric routing constraints as an atomic Boolean function. The generated Boolean function is satisfiable if and only if the corresponding routing is possible. Two different Boolean SAT-based routing models are analyzed: the track-based and the route-based routing constraint model. The track-based routing model transforms a routing task into a net-to-track assignment problem, whereas the route-based routing model reduces it into a routability-checking problem with explicitly enumerated set of detailed routes for nets. In both models, routing constraints are represented as CNF Boolean satisfiability clauses. Through comparative experiments, we demonstrate that the route-based formulation yields an easier-to-evaluate and more scalable routability Boolean function than the track-based method. This is empirical evidence that a smart/efficient Boolean formulation can achieve significant performance improvement in real-world applications.

Determining the depth of sequential circuits is a crucial step towards the completeness of bounded model checking proofs in hardware verification. In this paper, we formulate sequential depth computation as a logical inference problem for Quantified Boolean Formulas. We introduce a novel technique to simplify the complexity of the constructed formulas by applying simple transformations to the circuit netlist. We also study the structure of the resulting simplified QBFs and construct an efficient SAT-based algorithm to check their satisfiability. We report promising experimental results on some of the ISCAS 89 benchmarks.

Boolean satisfiability (SAT) solvers have experienced dramatic improvements in their performance and scalability over the last several years [5, 7] and are now routinely used in diverse EDA applications. Nevertheless, a number of practical SAT instances remain difficult to solve [9] and continue to defy even the best available SAT solvers [5, 7]. Recent work pointed out that symmetries in the Boolean search space are often to blame. A theoretical framework for detecting and breaking such symmetries was introduced in [2]. This framework was subsequently extended, refined, and empirically shown to yield significant speed-ups for a large number of benchmark classes in [1].Symmetries in the search space are broken by adding appropriate symmetry-breaking predicates (SBPs) to a SAT instance in conjunctive normal form (CNF). The SBPs prune the search space by acting as a filter that confines the search to non-symmetric regions of the space without affecting the satisfiability of the CNF formula. For symmetry breaking to be effective in practice, the computational overhead of generating and manipulating the SBPs must be significantly less than the run time savings they yield due to search space pruning. In this paper we present several new constructions of SBPs that improve on previous work. Specifically, we give a linear-sized CNF formula that selects lex-leaders (among others) for single permutations. We also show how that formula can be simplified by taking advantage of the sparsity of permutations. We test these improvements against earlier constructions and show that they yield smaller SBPs and lead to run time reductions on many benchmarks.

The MINCE heuristic for variable-ordering [1] can successfully reduce the size of BDDs and accelerate SAT-solving. Applications to reachability analysis have also been successful [12]. The main drawback of MINCE is its implementation complexity - the authors used a pre-existing min-cut placer [6] that is several times larger than any existing SAT solver. Tweaking MINCE is difficult.In this work we propose a replacement heuristic, FORCE which is easy to implement from scratch and tweak. It is dramatically faster than MINCE in practice. While FORCE may produce seemingly inferior variable orderings, the difference with MINCE orderings does not affect subsequent SAT-solving.

Research in algorithms for Boolean satisfiability (SAT) and their implementations (Goldberg and Novikov, 2002), (Moskewicz et al., 2001), (Silva and Sakallah, 1999) has recently outpaced benchmarking efforts. Most of the classic DIMACS benchmarks (ftp:dimacs.rutgers.edu/pub/challenge/sat/benchmarks/cnf ) can now be solved in seconds on commodity PCs. More recent benchmarks (Velev and Bryant, 2001) take longer to solve due to their large size, but are still solved in minutes. Yet, relatively small and difficult SAT instances must exist if P /spl ne/ NP. To this end, our paper articulates SAT instances that are unusually difficult for their size, including satisfiable instances derived from very large scale integration (VLSI) routing problems. With an efficient implementation to solve the graph automorphism problem (McKay, 1990), (Soicher, 1993) (Spitznagel, 1994), we show that in structured SAT instances, difficulty may be associated with large numbers of symmetries. We point out that a previously published symmetry extraction mechanism (Crawford et al., 1996) based on a reduction to the graph automorphism problem often produces many spurious symmetries. Our paper contributes two new reductions to graph automorphism, which extract all correct symmetries found previously (Crawford et al., 1996) as well as phase-shift symmetries not found earlier. The correctness of our reductions is rigorously proven, and they are evaluated empirically. We also formulate an improved construction of symmetry-breaking clauses in terms of permutation cycles and propose to use only generators of symmetries in this process. These ideas are implemented in a fully automated flow that first extracts symmetries from a given SAT instance, preprocesses it by adding symmetry-breaking clauses, and then calls a state-of-the-art backtrack SAT solver. Significant speed-ups are shown on many benchmarks versus direct application of the solver. In an attempt to further improve the practicality of our approach, we propose a scheme for fast "opportunistic" symmetry extraction and also show that considerations of symmetry may lead to more efficient reductions to SAT in the VLSI routing domain.

We introduce Satometer, a tool that can be used to estimate the percentage of the search space actually explored by a backtrack Boolean satisfiability (SAT) solver. Satometer calculates a normalized minterm count for those portions of the search space identified by conflicts. The computation is carried out using a zero-suppressed binary decision diagram data structure and can have adjustable accuracy. The data provided by Satometer can help diagnose the performance of SAT solvers and can shed light on the nature of a SAT instance.

Advances in methods for solving Boolean satisfiability (SAT) for large problems have motivated recent attempts to recast physical design problems as Boolean SAT problems. One persistent criticism of these approaches is their inability to supply partial solutions, i.e., to satisfy most but not all of the constraints cast in the SAT style. In this paper, we present a formulation for "subset satisfiable" Boolean SAT: we transform a "strict" SAT problem with N constraints into a new, "relaxed" SAT problem which is satisfiable just if not more than k/spl Lt/N of these constraints cannot be satisfied in the original problem. We describe a transformation based on explicit thresholding and counting for the necessary SAT relaxation. Examples from field-programmable gate-array routing show how we can determine efficiently when we can satisfy "almost all" of our geometric constraints.

There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic (CVSL), Pass Transistor Logic (PTL), and domino CMOS. Circuits designed in these noncomplementary ratioed logic families can be highly irregular, with complex diffusion sharing and nontrivial routing. Traditional digital cell layout synthesis tools derived from the highly stylized "functional cell" style break down when confronted with such circuit topologies. These cells require a full-custom, two-dimensional layout style which currently requires skilled manual design. In this work we propose a methodology for the synthesis of such complex noncomplementary digital cell layouts. We describe a new algorithm which permits the concurrent optimization of transistor chain placement and the ordering of the transistors within these diffusion-sharing chains. The primary mechanism for supporting this concurrent optimization is the placement of transistor subchains, diffusion-break-free components of the full transistor chains. When a chain is reordered, transistors may move from one subchain (and therefore one placement component) to another. We will demonstrate how this permits the chain ordering to be optimized for both intra-chain and inter-chain routing. We combine our placement algorithms with third-party routing and compaction tools, and present the results of a series of experiments which compare our technique with a commercial cell synthesis tool. These experiments make use of a new set of benchmark circuits which provide a rich sample of representative examples in several noncomplementary digital logic families.

Research in algorithms for Boolean satisfiability and their implementations [23, 6] has recently outpaced benchmarking efforts. Most of the classic DIMACS benchmarks [10] can be solved in seconds on commodity PCs. More recent benchmarks take longer to solve because of their large size, but are still solved in minutes [25]. Yet, small and difficult SAT instances must exist because Boolean satisfiability is NP-complete.We propose an improved construction of symmetry-breaking clauses [9] and apply it to achieve significant speed-ups over current state-of-the-art in Boolean satisfiability. Our techniques are formulated as pre-processing and can be applied to any SAT solver without changing its source code. We also show that considerations of symmetry may lead to more efficient reductions to SAT in the routing domain.Our work articulates SAT instances that are unusually difficult for their size, including satisfiable instances derived from routing problems. Using an efficient implementation to solve the graph automorphism problem [18, 20, 22], we show that in structured SAT instances difficulty may be associated with large numbers of symmetries.

We introduce Satometer, a tool that can be used to estimate the percentage of the search space actually explored by a backtrack SAT solver. Satometer calculates a normalized minterm count for those portions of the search space identified by conflicts. The computation is carried out using a zero-suppressed BDD data structure and can have adjustable accuracy. The data provided by Satometer can help diagnose the performance of SAT solvers and can shed light on the nature of a SAT instance.

We introduce a new approach to Boolean satisfiability (SAT) that combines backtrack search techniques and zero-suppressed binary decision diagrams (ZBDDs). This approach implicitly represents SAT instances using ZBDDs, and performs search using an efficient implementation of unit propagation on the ZBDD structure. The adaptation of backtrack search algorithms to such an implicit representation allows for a potential exponential increase in the size of problems that can be handled.

Optimized solvers for the Boolean Satisfiability (SAT) problem have many applications in areas such as hardware and software verification, FPGA routing, planning, etc. Further uses are complicated by the need to express "counting constraints" in conjunctive normal form (CNF). Expressing such constraints by pure CNF leads to more complex SAT instances. Alternatively, those constraints can be handled by Integer Linear Programming (ILP), but generic ILP solvers may ignore the Boolean nature of 0--1 variables. Therefore specialized 0--1 ILP solvers extend SAT solvers to handle these so-called "pseudo-Boolean" constraints.This work provides an update on the on-going competition between generic ILP techniques and specialized 0--1 ILP techniques. To make a fair comparison, we generalize recent ideas for fast SAT-solving to more general 0--1 ILP problems that may include counting constraints and optimization. Another aspect of our comparison is evaluation on 0--1 ILP benchmarks that originate in Electronic Design Automation (EDA), but that cannot be directly solved by a SAT solver. Specifically, we solve instances of the Max-SAT and Max-ONEs optimization problems which seek to maximize the number of satisfied clauses and the "true" values over all satisfying assignments, respectively. Those problems have straightforward applications to SAT-based routing and are additionally important due to reductions from Max-Cut, Max-Clique, and Min Vertex Cover. Our experimental results show that specialized 0--1 techniques tend to outperform generic ILP techniques on Boolean optimization problems as well as on general EDA SAT problems.

We apply recently introduced constructive multi-level synthesis in the resynthesis loop targeting convergence of industrial designs. The incremental ability of the resynthesis approach allows more predictable circuit implementations while allowing their aggressive optimization. The approach is based on a very general symbolic decomposition template for logic synthesis that uses information-theoretical properties of a function to infer its decomposition patterns (rather than more conventional measures such as literal counts). Using this template the decomposition is done in a Boolean domain unrestricted by the representation of a function, enabling superior implementation choices driven by additional technological constraints. The symbolic optimization is applied in resynthesis of industrial circuits which have tight timing constraints yielding their much improved timing properties.

Boolean functions are fundamental to synthesis and verification of digital logic, and compact representations of Boolean functions have great practical significance. Popular representations, such as CNF, DNF, circuits and ROBDDs [4], offer different advantages and are preferred for different tasks. Conversion between those representations is common, especially when one is used to represent the input and another speeds up relevant algorithms. Our work addresses the construction of ROBDDs that represent outputs of a given Boolean circuit. It is used in synthesis and verification. Earlier works (Fujita, Fujisawa, and Kawato, 1988. Malik et al., 1988.) proposed ordering circuit inputs and gates by graph traversals. We contribute orderings based on circuit partitioning and placement, leveraging the progress in recursive bisection and multi-level min-cut partitioning achieved in late 1990s. Our empirical results show that the proposed orderings based on circuit partitioning and placement are more successful than straightforward DFS and BFS, as well as related heuristics.

Advances in methods for solving Boolean satisfiability (SAT) for large problems have motivated recent attempts to recast physical design problems as Boolean SAT problems. One persistent criticism of these approaches is their inability to supply partial solutions, i.e, to satisfy most but not all of the constraints cast in the SAT style. In this paper we present a formulation for "subset satisfiable" Boolean SAT: we transform a "strict" SAT problem with N constraints into a new, "relaxed" SAT problem which is satisfiable just if not more than k << N of these constraints cannot be satisfied in the original problem. We describe a transformation based on explicit thresholding and counting for the necessary SAT relaxation. Examples from FPGA routing show how we can determine efficiently when we can satisfy "almost all" of our geometric constraints.

Boolean-based routing methods transform the geometric FPGA routing task into a large but atomic Boolean function with the property that any assignment of input variables that satisfies the function specifies a valid routing solution. We present a new search-based satisfiability (SAT) FPGA detailed routing formulation that handles all channels in an FPGA simultaneously. The formulation has the virtue that it considers all nets concurrently allowing higher degrees of freedom for each net, in contrast to the classical one-net-at-a-time approaches and is able to prove the unroutability of a given circuit by demonstrating the absence of a satisfying assignment to the routing Boolean function. To demonstrate the effectiveness of this method, we first present comparative experimental results between integer linear programming (ILP)-based routing, which is an alternative concurrent method, and SAT-based routing. We also present the. first comparisons of search-based Boolean SAT routing results to other conventional routers and offer the first evidence that SAT methods can actually demonstrate the unroutability of a layout. Preliminary experimental results suggest that our approach compares very favorably with both the ILP-based approach and conventional FPGA routers.

The existence of false paths represents a significant and computationally complex problem in the estimation of the true delay of combinational and sequential circuits. In this article we conduct a comprehensive study of modeling circuit delay computation, accounting for false paths, as a sequence of instances of Boolean satisfiability. Several path sensitization models and delay models are studied. In addition we evaluate some of the most competitive Boolean satisfiability algorithms seeking to identify which are best suited for solving circuit delay computation problems. Finally, realistic delay modeling (taking into account extracted interconnect delays and fanout data) is considered in order to experimentally evaluate the complexity of solving real-world instances.

We introduce a new verification methodology for modern micro-processors that uses a simple checker processor to validate the exe-cution of a companion high-performance processor. The checker can be viewed as an at-speed emulator that is formally verified to be compliant to an ISA specification. This verification approach en-ables the practical deployment of formal methods without impact-ing overall performance.

We introduce SATIRE, a new satisfiability solver that is particular-ly suited to verification and optimization problems in electronic de-sign automation. SATIRE builds on the most recent advances in satisfiability research, and includes two new features to achieve even higher performance: a facility for incrementally solving sets of related problems, and the ability to handle non-CNF constraints. We provide experimental evidence showing the effectiveness of these additions to classical satisfiability solvers.

To address the problem of accurate timing characterization, this paper proposes a method that fully exploits mode dependency. It is based on the premise that circuit delays are determined largely by a set of control inputs for which the number of useful combinations, i.e., modes, is small for most practical circuits. We take the mode-dependent characterization approach further and enhance it so that the delays of the I/O paths between the control inputs and outputs are calculated more accurately. We prove that, with a careful choice of propagation conditions, our method can generate timing models with very tight path delays that are guaranteed to give correct results. Experimental results using real-life circuits show that cir-cuit delays can vary significantly among different modes for both control and data input delays, and capturing this variation can have a significant impact on the overall system timing.

Incremental redesign is an increasingly essential step in any complex design. Late changes or corrections in functional specifications (so-called "engineering change orders" or ECOs) force us to search for a minimal perturbation that achieves the desired repair. In reconfigurable design scenarios, these incremental repairs may be in response to physical faults: the goal is to "design around" the fault. For FPGAs, incremental rerouting is an essential component of this repair problem. We have developed a new incremental rerouting algorithm for FPGAs using techniques from Boolean Satisfiability (SAT). In this application, these techniques have the twin virtues that they (1) represent all possible routing (and rerouting) constraints simultaneously and exactly, and (2) search for rerouting solutions by perturbing all nets concurrently. Preliminary results are promising. For several FPGA benchmarks, we were able to reroute fault reconfigurations that perturb up to 5.74% of all nets for a small number of fault sets (one to four faults) with only 1.55 track overhead per channel on average, with CPU time 0.76 to 4.91 seconds/fault.

The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponential in the worst-case, the structure of real-world instances is a natural source of improvements. While SAT and BDD techniques are often presented as mutually exclusive alternatives, our work points out that both can be improved via the use of the same structural properties of instances. Our proposed methods are based on efficient problem partitioning and can be easily applied as pre-processing with arbitrary SAT solvers and BDD packages without source code modifications. Our contribution is validated on the ISCAS circuits and the DIMACS benchmarks. Empirically, our technique often outperforms existing techniques by a factor of two or more. Our results motivate search for stronger dynamic ordering heuristics and combined static/dynamic techniques.

A Boolean-based router expresses the routing constraints as a Bool?ean function which is satisfiable if and only if the layout is routable. Compared to traditional routers, Boolean-based routers offer two unique features: (1) simultaneous embedding of all nets regardless of net ordering, and (2) ability to demonstrate routing infeasibility by proving the unsatisfiability of the generated routing constraint Boolean function. In this paper, we introduce a new Boolean-based FPGA detailed routing formulation that yields an easy-to-evaluate and more scalable routability Boolean function than the previous methods. The routability constraints are expressed in terms of a set of route variables each of which designating a specific detailed route for a given net. Experimental results clearly show the superi?ority of this formulation over an earlier formulation that expressed the constraints in terms of track variables.

In deep submicrometer integrated circuit design, there is a growing need to quickly and accurately characterize the timing of large circuit blocks. Accurate timing characterization requires making available as much timing information as possible at each step of the design process. Conventional fast characterization methods typically employ topological analysis, which can be inaccurate because of its inability to eliminate false paths. To address this problem, a new method for creating accurate timing models of circuit blocks by making efficient use of their functionality is introduced. The proposed mode-dependent characterization (ModeChar) method is based on calculating a distinct timing model for each mode of circuit operation and reflects the way practical circuits function. ModeChar produces a mode-dependent timing model that contains delay information for a given set of circuit modes. It is shown that circuit delays are never underestimated by the mode-dependent models. The concept of mode dependency is taken further by extending it to sequential circuits. Given a sequential circuit, a compact set of constraints is derived for each circuit mode that captures all the timing constraints that must be satisfied for correct operation of the circuit. Experimental results are presented that demonstrate the effectiveness of ModeChar in eliminating many false paths that would otherwise result in performance penalties. In addition, our experiments indicate that delays can vary considerably among circuit modes, making conventional topological analysis overly pessimistic. To make the mode-dependent models more compact, an efficient algorithm far coalescing delay information is also introduced.

Boolean Satisfiability (SAT) is often used as the underlying model for a significant and increasing number of applications in Electronic Design Automation (EDA) as well as in many other fields of Computer Science and Engineering. In recent years, new and efficient algorithms for SAT have been developed, allowing much larger problem instances to be solved. SAT “packages” are currently expected to have an impact on EDA applications similar to that of BDD packages since their introduction more than a decade ago. This tutorial paper is aimed at introducing the EDA professional to the Boolean satisfiability problem. Specifically, we highlight the use of SAT models to formulate a number of EDA problems in such diverse areas as test pattern generation, circuit delay computation, logic optimization, combinational equivalence checking, bounded model checking and functional test vector generation, among others. In addition, we provide an overview of the algorithmic techniques commonly used for solving SAT, including those that have seen widespread use in specific EDA applications. We categorize these algorithmic techniques, indicating which have been shown to be best suited for which tasks.

The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has been typically applied to EDA as follows: (1) formulation of the given problem as a SAT instance (2) solution of the SAT instance. In this paper we present a method to simultaneously solve several closely related SAT instances using incremental satisfiability (ISAT). In ISAT, the decision sequence made for a "prefix" function is used to solve another set of functions which have a number of new constraints (extensions) added to the prefix function. Our experiments show that we can achieve significant gains in total runtime when we use this methodology as opposed to resetting the decision sequences and solving each instance from scratch. Application of ISAT to delay fault testing is presented by formulating incremental path sensitization as an ISAT problem. Non-robust tests for the combinational portion of ISCAS 89 circuits are generated using this method.

In this paper a constructive library-aware multilevel logic synthesis approach using symmetries is described. It integrates the technology-independent and technology dependent stages of synthesis, and is premised on the goal of relating the functional structure of a logic specification closer to the ultimate topological and physical structures. We show that symmetries interpreted as structural attributes of functions can be effectively used to induce a favorable structural implementation. These symmetries are used in bridging (1) the structural properties of the functions being synthesized, (2) the structural attributes of the implementation network, and (3) the functional content of the target library. Experimental results show that the quality of circuits synthesized using this approach is generally superior to those synthesized by traditional approaches, and that the improvement correlates with the symmetry measure in a function.

Interest in propositional satisfiability (SAT) has been on the rise lately, spurred in part by the recent availability of powerful solvers that are sufficiently efficient and robust to deal with the large-scale SAT problems that typically arise in electronic design automation application. A frequent question that CAD tool developers and users typically ask is which of these various solvers is "best"; the quick answer is, of course, "it depends". In this paper we attempt to gain some insight into, rather than definitively answer, this question.

In this paper we take a fresh look at the notion of symmetries in Boolean functions. Our studies are motivated by the fact that the classical characterization of symmetries based on invariance under variable swaps is a special case of a more general invariance based on unrestricted variable permutations. We propose a generalization of classical symmetry that allows for the simultaneous swap of ordered and unordered groups of variables, and show that it captures more of a function's invariant permutations without undue computational requirements. We apply the new symmetry definition to analyze a large set of benchmark circuits and provide extensive data showing the existence of substantial symmetries in those circuits. Specific case studies of several of these benchmarks reveal additional insights about their functional structure and how it might be related to their circuit structure.

Boolean satisfiability (SAT) and its application to a number of electronic design automation (EDA) problems have been the topic of extensive study over the lost couple of decades. In many cases, a set of related SAT problems need to be solved in order to obtain an answer to a given application-specific problem. Incremental satisfiability (ISAT) refers to solving a set of related SAT problems by augmenting a previously solved problem with additional constraints, thereby reusing previous decision sequences. In this paper, we present a new ISAT engine that supports both the addition and removal of constraints. This can be achieved by keeping track of the relationships between constraints. We identify and define a special type of ISAT that occurs frequently in the context of path sensitization called stack-based ISAT and define the structure of this as a problem tree. In this type of ISAT constraints are allowed to be added and removed only in last-in first-out (LIFO) order. We also introduce a solution caching mechanism to expedite the search by recording and retrieving solutions to intermediate nodes in a problem tree.

A method that characterizes the timing of Intellectual Property (ZP) blocks while taking into account IP functionality is presented.IP blocks are assumed to have multiple modes of operation specified by the user.For each mode, our method calculates IO path delays and timing constraints to generate a timing model.The method thus captures the mode-dependent variation in IP delays which, according to our experiments, can be as high as 90%.The special manner in which delay calculation is performed guarantees that IP delays are never underestimated.The resulting timing models are also compacted through a process whose accuracy is controlled by the user.1.1

lier BDD-based methods.Boolean-based routing transforms the geometric FPGA routing task into a single, large Boolean equation with the property that any assignment of input variables that "satisfies" the equation (that renders equation identically "1") specifies a valid routing.The formulation has the virtue that it considers all nets simultaneously, and the absence of a satisfying assignment implies that the layout is unroutable.Initial Boolean-based approaches to routing used Binary Decision Diagrams (BDDs) to represent and solve the layout problem.BDDs, however, limit the size and complexity of the FPGAs that can be routed, leading these approaches to concentrate only on individual FPGA channels.In this paper, we present a new search-based Satisfiability (SAT) formulation that can handle entire FPGAs, routing all nets concurrently.The approach relies on a recently developed SAT engine (GRASP) that uses systematic search with conflict-directed non-chronological backtracking, capable of handling very large SAT instances.We present the first comparisons of search-based SAT routing results to other routers, and offer the first evidence that SAT methods can actually demonstrate the unroutability of a layout.Preliminary experimental results suggest that this approach to FPGA routing is more viable than ear-1.1

Abstract : The automated synthesis of mask geometry for VLSI leaf cells, referred to as the cell synthesis problem, is an important component of any structured custom integrated circuit design environment. Traditional approaches based on the classic functional cell style of Uehara & VanCleemput pose this problem as a straightforward one-dimensional graph optimization problem for which optimal solution methods are known. However, these approaches are only directly applicable to static CMOS circuits and they break down when faced with more exotic logic styles. Our methodology is centered around techniques for the efficient modeling and optimization of geometry sharing. Chains of diffusion-merged transistors are formed explicitly and their ordering optimized for area and global routing. In addition, more arbitrary merged structures are supported by allowing electrically compatible adjacent transistors to overlap during placement. The synthesis flow in TEMPO begins with a static transistor chain formation step. These chains are broken at the diffusion breaks and the resulting sub-chains passed to the placement step. During placement, an ordering is found for each chain and a location and orientation is assigned to each sub-chain. Different chain orderings affect the placement by changing the relative sizes of the sub-chains and their routing contribution. We conclude with a detailed routing step and an optional compaction step.

This paper introduces GRASP (Generic seaRch Algorithm for the Satisfiability Problem), a new search algorithm for Propositional Satisfiability (SAT). GRASP incorporates several search-pruning techniques that proved to be quite powerful on a wide variety of SAT problems. Some of these techniques are specific to SAT, whereas others are similar in spirit to approaches in other fields of Artificial Intelligence. GRASP is premised on the inevitability of conflicts during the search and its most distinguishing feature is the augmentation of basic backtracking search with a powerful conflict analysis procedure. Analyzing conflicts to determine their causes enables GRASP to backtrack nonchronologically to earlier levels in the search tree, potentially pruning large portions of the search space. In addition, by "recording" the causes of conflicts, GRASP can recognize and preempt the occurrence of similar conflicts later on in the search. Finally, straightforward bookkeeping of the causality chains leading up to conflicts allows GRASP to identify assignments that are necessary for a solution to be found. Experimental results obtained from a large number of benchmarks indicate that application of the proposed conflict analysis techniques to SAT algorithms can be extremely effective for a large number of representative classes of SAT instances.

This paper addresses static timing verification for sequential circuits implemented in a mix of static and dynamic logic. We restrict our focus to regular domino logic and footless domino logic, a variant of domino logic. First we derive constraints for proper operation of dynamic gates. An important observation is that for dynamic gates, input signals may start changing near the end of the evaluate phase without compromising correct operation. This gives the circuit designer extra flexibility. We present two verification methods. Both are based on the Sakallah-Mudge-Olukotun (SMO) model for static timing analysis of sequential circuits. The first method models dynamic gates explicitly. The signals at the terminals of the dynamic gates are modeled by five events: the earliest/latest, rising/falling transitions, and a fifth event that models the occurrence of a spurious rising transition. The second method applies the original SMO model after a preprocessing step that computes the combinational delays. A postprocessing step checks the constraints specific to dynamic gates. The relationship between both methods is studied. We show that the second method may result in a more conservative analysis than the first method, but at a lower computational cost. We also examine a less aggressive set of constraints, which disallows spurious transitions. A detailed example illustrating the important features of the model is presented, and an electrical simulation of that circuit is performed. The results demonstrate the practical relevance of the methods.

We describe a new constructive multilevel logic synthesis system that integrates the traditionally separate technology-independent and technology-dependent stages of modern synthesis tools. Dubbed M32, this system is capable of generating circuits incrementally based on both functional as well as structural considerations. This is achieved by maintaining a dynamic structural representation of the evolving implementation and by refining it through progressive introduction of gates from a target technology library. Circuit construction proceeds from the primary inputs towards the primary outputs. Preliminary experimental results show that circuits generated using this approach are generally superior to those produced by multi-stage synthesis.

This paper introduces and demonstrates an extension to quadratic placement that accounts for wiring congestion. The algorithm uses an A* router and line-probe heuristics on region-based routing graphs to compute routing cost. The interplay between routing analysis and quadratic placement using a growth matrix permits global treatment of congestion. Further reduction in congestion is obtained by the relaxation of pin constraints. Experiments show improvements in wireability.

Despite its importance, we find that a rigorous theoretical foundation for performing timing analysis has been lacking so far. As a result, we have initiated a research project that aims to provide such a foundation for functional timing analysis. As part of this work we have developed an abstract automaton based delay model that accounts for the various analog factors affecting delay, such as signal slopes, near simultaneous switching, etc., while at the same rime accounting for circuit functionality. This paper presents this delay model.

A model for integrated circuit design rules based on rectangle edge constraints has been proposed by Jeppson, Christensson, and Hedenstierna. This model appears to be the most rigorous proposed to date for the description of such edge-based design rules. However, in certain rare circumstances their model is unable to express the correct design rule when the constrained edges are not adjacent in the layout. We introduce a new notation, called an edge path, which allows us to extend their model to allow for constraints between edges separated by an arbitrary number of intervening edges. Using this notation we enumerate all edge paths that are required to correctly model the original design rule macros of the JCH model, and prove that these macros are sufficient to model the most common rules. We also show how this notation alows us to directly specify many kinds of conditional design rules that required ad hoc specification under the JCH model.

A self-aligned complementary GaAs (CGaAs) technology (developed at Motorola) for low-power, portable, digital and mixed-mode circuits is being extended to address high-speed VLSI circuit applications. The process supports full complementary, unipolar (pseudo-DCFL), source-coupled, and dynamic (domino) logic families. Though this technology is not yet mature, it is years ahead of CMOS in terms of fast gate delays at low power supply voltages. Complementary circuits operating at 0.9 V have demonstrated power-delay products of 0.01 /spl mu/W/MHz/gate. Propagation delays of unipolar circuits are as low as 25 ps. Logic families can be mixed on a chip to trade power for delay. CGaAs is being evaluated for VLSI applications through the design of a PowerPC-architecture microprocessor.

While delay modeling of gates with a single switching input has received considerable attention, the case of multiple inputs switching in close temporal proximity is just beginning to be addressed in the literature.The effect of proximity of input transitions can be significant on the delay and output transition time.The few attempts that have addressed this issue are based on a series-parallel transistor collapsing method that reduces the multi-input gate to an inverter.This limits the technique to CMOS technology.Moreover, none of them discuss the appropriate choice of voltage thresholds to measure delay for a multi-input gate.In this paper, we first present a method for the choice of voltage thresholds for a multi-input gate that ensures a positive value of delay under all input conditions.We next introduce a dual-input proximity model for the case when only two inputs of the gate are switching.We then propose a simple approximate algorithm for calculating the delay and output transition time that makes repeated use of the dual-input proximity model without collapsing the gate into an equivalent inverter.Comparison with simulation results shows that our method performs quite well in practice.

Two methods are presented for static timing verification of sequential circuits implemented as a mix of static and domino logic. Constraints for proper operation of domino gates are derived. An important observation is that input signals to domino gates may start changing near the end of the evaluate phase. The first method models domino gates explicitly, similar to latches. The second method treats domino gates only during pre- and post-processing steps. This method is shown to be more conservative, but easier to compute.

This paper introduces GRASP (Generic seaRch Algorithm for the Satisfiability Problem), an integrated algorithmic framework for SAT that unifies several previously proposed search-pruning techniques and facilitates identification of additional ones. GRASP is premised on the inevitability of conflicts during search and its most distinguishing feature is the augmentation of basic backtracking search with a powerful conflict analysis procedure. Analyzing conflicts to determine their causes enables GRASP to backtrack non-chronologically to earlier levels in the search tree, potentially pruning large portions of the search spare. In addition, by "recording" the causes of conflicts, GRASP can recognize and preempt the occurrence of similar conflicts later on in the search. Finally straightforward bookkeeping of the causality chains leading up to conflicts allows GRASP to identify assignments that are necessary for a solution to be found. Experimental results obtained from a large number of benchmarks, including many from the field of test pattern generation, indicate that application of the proposed conflict analysis techniques to SAT algorithms can be extremely effective for a large number of representative classes of SAT instances.

We present a novel timing analysis method ACD that computes an approximate value for the delay of datapath circuits. Based on the conditional delay matrix (CDM) formalism we introduced earlier the ACD method exploits the fact that most datapath signals are directed by a small set of control inputs. The signal propagation conditions are restricted to a set of predefined central inputs, which results in significant reductions in the size of the conditions as well as computation time. We have implemented ACD and experimented with reverse-engineered high-level versions of the ISCAS-85 benchmarks. Our results demonstrate up to three orders of magnitude speedup in computation time over exact methods, with little or no loss in accuracy.

Introduces GRASP (Generic seaRch Algorithm for the Satisfiability Problem), a new search algorithm for propositional satisfiability (SAT). GRASP incorporates several search-pruning techniques, some of which are specific to SAT, whereas others find equivalent in other fields of artificial intelligence. GRASP is premised on the inevitability of conflicts during a search, and its most distinguishing feature is the augmentation of the basic backtracking search with a powerful conflict analysis procedure. Analyzing conflicts to determine their causes enables GRASP to backtrack non-chronologically to earlier levels in the search tree, potentially pruning large portions of the search space. In addition, by "recording" the causes of conflicts, GRASP can recognize and preempt the occurrence of similar conflicts later on in the search. Finally, straightforward bookkeeping of the causality chains leading up to conflicts allows GRASP to identify assignments that are necessary for a solution to be found. Experimental results obtained from a large number of benchmarks indicate that application of the proposed conflict analysis techniques to SAT algorithms can be extremely effective for a large number of representative classes of SAT instances.

Ravel-XL is a single-board hardware accelerator for gate-level digital logic simulation. It uses a standard levelized-code approach to statically schedule gate evaluations. However, unlike previous approaches based on levelized-code scheduling, it is not limited to zero- or unit-delay gate models and can provide timing accuracy comparable to that obtained from event-driven methods. We review the synchronous waveform algebra that forms the basis of the Ravel-XL simulation algorithm, present an architecture for its hardware realization, and describe an implementation of this architecture as a single VLSI chip. The chip has about 900000 transistors on a die that is approximately 1.4 cm/sup 2/, requires a 256 pin package and is designed to run at 33 MHz. A Ravel-XL board consisting of the processor chip and local instruction and data memory can simulate up to one billion gates at a rate of approximately 6.6 million gate evaluations per second. To better appreciate the tradeoffs made in designing Ravel-XL, we compare its capabilities to those of other commercial and research software simulators and hardware accelerators.

Article The Aurora RAM compiler Share on Authors: Ajay Chandna University of Michigan, Department of Electrical Engineering & Computer Science, Ann Arbor, MI University of Michigan, Department of Electrical Engineering & Computer Science, Ann Arbor, MIView Profile , C. David Kibler Hewlett Packard Company, 3404 East Harmony Rd., Ft. Collins, CO Hewlett Packard Company, 3404 East Harmony Rd., Ft. Collins, COView Profile , Richard B. Brown University of Michigan, Department of Electrical Engineering & Computer Science, Ann Arbor, MI University of Michigan, Department of Electrical Engineering & Computer Science, Ann Arbor, MIView Profile , Mark Roberts University of Michigan, Department of Electrical Engineering & Computer Science, Ann Arbor, MI University of Michigan, Department of Electrical Engineering & Computer Science, Ann Arbor, MIView Profile , Karem A. Sakallah University of Michigan, Department of Electrical Engineering & Computer Science, Ann Arbor, MI University of Michigan, Department of Electrical Engineering & Computer Science, Ann Arbor, MIView Profile Authors Info & Claims DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation ConferenceJanuary 1995 Pages 261–266https://doi.org/10.1145/217474.217539Online:01 January 1995Publication History 0citation326DownloadsMetricsTotal Citations0Total Downloads326Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Aggressive design using level-sensitive latches and wave pipelining has been proposed to meet the increasing need for higher performance digital systems. The optimal clocking problem for such designs has been formulated using an accurate timing model. However, this problem has been difficult to solve because of its nonconvex solution space. The best algorithms to date employ linear programs to solve an overconstrained case that has a convex solution space, yielding suboptimal solutions to the general problem. A new efficient (cubic complexity) algorithm, Gpipe, exploits the geometric characteristics of the full nonconvex solution space to determine the maximum single-phase clocking rate for a closed pipeline with a specified degree of wave pipelining. Introducing or increasing wave pipelining by permanently enabling some latches is also investigated. Sufficient conditions have been found to identify which latches can be removed in this fashion so as to guarantee no decrease and permit a possible increase in the clock rate. Although increasing the degree of wave pipelining can result, in faster clocking, wave pipelining is often avoided in design due to difficulties in stopping and restarting the pipeline under stall conditions without losing data or in reduced rate testing of the circuit. To solve this problem, which has not previously been addressed, we present conditions and implementation methods that insure the stoppability and restartability of a wave pipeline.

In this paper we derive delay and transition time macromodels for GaAs DCFL logic gates. The macromodels are derived by a systematic application of dimensional analysis aimed at finding suitable minimal functional forms that capture the effects of all relevant parameters. The process is illustrated through a detailed step-by-step account of the macromodel development for DCFL inverters. Based on different modeling approximations, one- and two-argument macromodel functions are derived and compared. The inverter macromodel is then used as a basis for developing timing macromodels for superbuffers and NOR gates. The NOR gate macromodels account for the simultaneous and near-simultaneous switching of two inputs, with an extension to multiple inputs.>

This paper extends the classical notion of critical paths in combinational circuits to the case of synchronous circuits that use level-sensitive latches. Critical paths in such circuits arise from setup, hold, and cyclic constraints on the data signals at the inputs of each latch and may extend through one or more latches. Two approaches are presented for identifying these critical paths and verifying their timing. The first implicitly checks all paths using a relaxation-based solution procedure. Results of this procedure are used to calculate slack values, which in turn identify satisfied and violated critical paths. The second approach is based on a constructive algorithm which generates all the critical paths in a circuit and then verifies that their timing constraints are satisfied. Algorithms are evaluated and compared using circuits from the ISCAS89 sequential benchmark suite and the Michigan High Performance Microprocessor Project.>

Abstract — A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path sensitization can be posed as a search, in the n-dimensional Boolean space, for a consistent assignment of logic values to the circuit nodes which also satisfies a given condition. In this paper we propose and demonstrate the effectiveness of several new techniques for search-space pruning for test pattern generation. In particular, we present linear-time algorithms for dynamically identifying unique sensitization points and for dynamically maintaining reduced head line sets. In addition, we present two powerful mechanisms that drastically reduce the number of backtracks: failure-driven assertions and dependency-directed backtracking. Both mechanisms can be viewed as a form of learning while searching and have analogs in other application domains. These search pruning methods have been implemented in a generic path sensitization engine called LEAP. A test pattern generator, TG-LEAP, that uses this engine was also developed. We present experimental results that compare the effectiveness of our proposed search pruning strategies to those of PODEM, FAN, and SOCRATES. In particular, we show that LEAP is very efficient in identifying undetectable faults and in generating tests for difficult faults. I.

We present a procedure, based on dimensional analysis, to simplify macromodeling. By combining variables according to their units, simpler equations involving dimensionless variables can be derived. The procedure is illustrated by developing macromodels for power dissipation, supply current, and propagation delay of a CMOS inverter.>

This paper describes a new path sensitization model in which search-space pruning techniques commonly used in test pattern generation can be applied to timing analysis. A safe static sensitization criterion, equivalent to floating-mode sensitization, is proposed and represented in the new path sensitization model. This model has been used to implement a timing analysis tool, TA-LEAP, and preliminary results indicate significant performance gains over previous methods.>

This paper discusses a mathematical optimization problem with a number of applications in the timing analysis of synchronous and asynchronous circuits. This problem, which we call min-max linear programming (mmLP), involves the solution of linear programs that have min and max functions added to their constraints. Instances of problem mmLP are described, and a simple proof of NP-completeness is given. Two alternate methods are presented for mmLP solution. The first uses a branch-and-bound algorithm which is optimized to specifically reduce the number of operations required by the simplex linear programming algorithm. The second uses a transformation to a standard mixed integer linear programming (MILP) formulation. We evaluate both approaches on a variety of problems, including several large previously unsolved optimal clocking problems.

We describe the design of Ravel-XL, a hardware accelerator for assigned-delay compiled-code logic gate simulation. After a brief review of the underlying Ravel simulation algorithm, we describe the major factors that influenced the hardware design, particularly the interaction between the instruction execution and operand bandwidth requirements. The initial CMOS VLSI implementation of the accelerator contains a 2K word data cache, occupies approximately 1.9 cm/sup 2/ of die area with 256 pins and approximately 900,000 transistors. Simulation results predicts operation at a clock rate of 33 MHz. This provides a speedup of about 50 over the software implementation of Ravel, about 50 over a compiled event-driven simulator, and about 500 over an interpreted event-driven simulator. We conclude with some planned design improvements that will allow an approximate doubling of the clock rate.>

We introduce a new framework for describing path sensitization criteria in combinational networks. This framework is used to analyze and categorize several sensitization criteria proposed in the past. We discuss some misconceptions of existing sensitization criteria, and evaluate the effects of hazards on the delay of combinational circuits. Finally, we introduce a new sensitization criterion representing a lower bound on the delay of the longest sensitizable path.>

A recently formulated general timing model of synchronous operation is applied to the special case of latch-controlled pipelined circuits. The model accounts for multiphase synchronous clocking, correctly captures the behavior of label-sensitive latches, handles both short- and long-path delays, accommodates wave pipelining, and leads to a comprehensive set of timing constraints. Concurrency of pipeline circuits is defined as a function of the clock schedule and degree of wave pipelining. The authors then identify a special class of clock schedules, coincident multiphase clocks, which provide a lower bound on the value of the optimum cycle time. It is shown that the region of feasible solutions for single-phase clocking can be nonconvex or even disjoint, and a closed-form expression for the minimum cycle time of a restricted but practical form of single-phase clocking is derived. The authors compare these forms of clocking on three pipeline examples and highlight some of the issues in pipeline synchronization.>

An approach to timing verification of circuits with level-sensitive latches which focuses on the critical paths that constrain the operating speed of these circuits is described. The timing model used has been referred to as the 'SMO model' (Sakallah, Mudge and Olukotun, 1990). Three types of critical paths (long, short and loops) can arise in the SMO formulation; verifying their timing is sufficient to ensure correct operation. An algorithm for identifying these paths is presented, and its relationship to other approaches to solving the SMO model equations is discussed. Finally, results which demonstrate the algorithm on circuits from the ISCAS89 benchmark suite are presented.>

Geometric knowledge of the shape of the feasible region formed by pulse width, setup, and hold constraints is used directly by an efficient (cubic complexity) algorithm, Gpipe, to determine the maximum rate for single-phase clocking of a given pipeline. The pipeline model uses level-sensitive latches as synchronizers and can allow wave pipelining. Gpipe is also used to explore the effect of removing nonsynchronizing and/or synchronizing latches on the maximum clock speed of the pipeline. A simple test shows which latches, if any, to remove in order to guarantee no decrease, and permit a possible increase, in the clock rate.>

Ravel, a long- and short-path delay-accurate compiled-code logic gate simulator suitable for both the functional and timing verification of multiphase synchronous circuits, is described. It is based on a waveform model of synchronous operation and an associated algebra for combining such waveforms both logically and temporally. This algebra extends the range of compiled-code simulation, which has been limited in the past to static functional verification, so that dynamic signal propagation effects can be captured accurately. For synchronous circuits exhibiting significant event activity per clock cycle, Ravel simulation can be faster than traditional event-driven simulation with no sacrifice in the delay modeling accuracy. Initial experiments with Ravel on a subset of the ISCAS 89 sequential benchmarks confirm its viability as an alternative to event-driven simulation.>

The authors present a succinct formulation of the timing constraints for latch-controlled synchronous digital circuits. It is shown that the constraints are mildly nonlinear. The equivalence of the nonlinear optimal cycle time calculation problem to an associated and simpler linear programming (LP) problem is proved. A LP-based algorithm which is guaranteed to obtain the optimal cycle time for arbitrary circuits controlled by a general class of multiphase overlapped clocks is presented. The formulation and an initial implementation of the algorithm on some example circuits are illustrated.>

The authors introduce a novel circuit model that accurately represents the temporal behavior of combinational circuits. This circuit model is the basis for the derivation of a new sensitizing criterion which provides the necessary conditions for accurate timing analysis. The authors describe the FPD timing analysis environment supported by the sensitizing criterion and present examples of its application.>

A timing model for circular pipelines is presented and used to obtain the minimum cycle time in terms of circuit delays and clock skews. The model accounts for short- and long-path delays, the effects of clock skew, and the use of both latches and flip-flops as synchronizing elements. The formulation and implementation of algorithms to find the minimum cycle time for both single-phase and a restricted class of multi-phase clocks are described.>

We present a succinct formulation of the timing constraints for latch-controlled synchronous digital circuits. We show that the constraints are mildly nonlinear, and prove the equivalence of the nonlinear optimal cycle time calculation problem to an associated and simpler linear programming (LP) problem. We present an LP-based algorithm which is guaranteed to obtain the optimal cycle time for arbitrary circuits controlled by a general class of multi-phase overlapped clocks. We illustrate the formulation and an initial implementation of the algorithm on some example circuits.

Two CAD tools, checkT/sub c/ and minT/sub c/, for timing verification and optimal clocking are introduced. Both tools are based on a new timing model of synchronous digital circuits. The model has the following features: (1) it is general enough to handle arbitrary multiphase clocking; (2) complete, in the sense that it captures signal propagation along short as well as long paths in the logic; (3) extensible to make it relatively easy to incorporate 'complex' latching structures; and (4) notationally simple to make it amenable to analytic treatment in some important special cases. These tools are being used to help in the design of a 4 ns gallium arsenide micro-supercomputer.>

The Meyer capacitance model (see RCA Rev., vol.32, p.42-63, 1971) fails to obey the charge conservation law. It is shown that the charge nonconservation in the Meyer model is not due to any physical assumptions. Rather, it is caused by the mathematical error of characterizing a multidimensional function (the stored charge on the four terminals of a MOSFET) by an incomplete subset of its partial derivatives (the partial derivatives of the gate charge). This conclusion is supported by developing and implementing a correct mathematical characterization of the MOS charges based on the same physical assumptions used in the Meyer model. One important outcome of this exercise is that the nonreciprocal nature of MOS capacitive coupling is evident even in a first-order physical model of the device.>

This paper describes the circuit simulation algorithms of the SAMSON2 mixed circuit/logic simulator. SAMSON2 employs event driven simulation techniques to exploit the inherent temporal sparseness in VLSI circuits. At the circuit level, SAMSON2 can be more than an order of magnitude faster than a "standard" circuit simulator such as SPICE2 while providing comparable waveform accuracy. This performance is achieved by partitioning a circuit into subcircuits which are allowed to have separate integration step sizes reflecting their activity level. The accuracy of the solution is maintained by controlling the errors due to decoupling among the subnetworks as well as the local truncation within each subnetwork. Simulation examples of typical MOS integrated circuits (IC's) are presented. f