Dong Hyeon Cheon

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2ranked-venue papers

0as first author

0since 2021 · last 2000

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Security and privacy · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems 1 paper		Integrated circuit design · 100%
Network and information security 1 paper		Cryptographic primitives and cryptanalysis · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Integrated circuit design finite field arithmetic	1	2000	Efficient Normal Basis Multipliers in Composite Fields · IEEE Trans. Computers 2000
Integrated circuit design › finite field arithmetic › finite field multiplier normal basis multiplier	1	2000	Efficient Normal Basis Multipliers in Composite Fields · IEEE Trans. Computers 2000
Cryptographic primitives and cryptanalysis › cryptographic implementation hardware implementation	1	2000	Efficient Normal Basis Multipliers in Composite Fields · IEEE Trans. Computers 2000

Methods — techniques the papers use, named apart from their topics

bit-parallel multiplication · 0.1

Year	Publication	Venue	Position
2000	Provable Security against Differential and Linear Cryptanalysis for the SPN Structure Seokhie Hong, Sangjin Lee 0002, Jongin Lim 0001, Jaechul Sung, Dong Hyeon Cheon, Inho Cho	FSE	5
2000	Efficient Normal Basis Multipliers in Composite Fields abstract It is well-known that a class of finite fields GF(2/sup n/) using an optimal normal basis is most suitable for a hardware implementation of arithmetic in finite fields. In this paper, we introduce composite fields of some hardware-applicable properties resulting from the normal basis representation and the optimal condition. We also present a hardware architecture of the proposed composite fields including a bit-parallel multiplier. Sangho Oh, Chang Han Kim, Jongin Lim 0001, Dong Hyeon Cheon	IEEE Trans. Computers	4