A programmable single-chip multiprocessor system for video coding applications has been developed. It integrates four processing elements, on-chip DRAM, and application-specific interfaces. The integrated DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing element.

The video signal processor AxPe1280V has been developed forimplementation of different video coding applications accordingto standards like ITU-T H.261/H.263, and ISO MPEG-1/2.Itconsists of a RISC processor supplemented by a coprocessor forconvolution-like low-level tasks.RISC and coprocessor have beenimplemented in a standard cell design combined with full-custommodules.The processor was fabricated in a 0.5 µm CMOS technologyand has a die size of 82 mm{2}.It provides a peak performanceof more than 1 giga arithmetic operations per second (GOPS) at66 MHz.For processing of very computation-intensive algorithmsor high data rates, several processors can be bus-connected to forma MIMD multiprocessor system.

The architecture and implementation of a programmable video signal processor dedicated as building block of a multiple instruction multiple data (MIMD)-based bus-connected multiprocessor system is presented. This system can either be constructed from several single processor chips, or it can be integrated on a large area integrated circuit containing several processors. The processor allows an efficient implementation of different video coding standards like H.261, H.263, MPEG-1 and MPEG-2. It consists of a RISC processor supplemented by a coprocessor for computation intensive convolution-like tasks, which provides a peak performance of more than 1 giga-arithmetic operations per second (GOPS). A large area integrated circuit integrating 9 processor elements (PE's) on an area of 16.6 cm/sup 2/ has been designed. Due to yield considerations redundancy concepts have been implemented, that-even in the presence of production defects-result in working chips utilizing a lower number of PE's. Each PE has built-in self-test (BIST) capabilities, which allow for an independent test of itself under the control of its integrated fault-tolerant BIST controller. Defective PE's are switched off. Only the PE's passing the BIST are used for video processing tasks. Prototypes have been fabricated in a 0.8 /spl mu/m complementary metal-oxide-semiconductor (CMOS) process structured by masks using wafer stepping with overlapping exposures. Employing redundancy, up to 6 PE's per chip were functional at 66 MHz, thus providing a peak arithmetic performance of up to 6 GOPS.