We have developed a completely automated approach to hardware design based on integrating three core technologies into one comprehensive system, namely genetic programming (GP), the VHSIC Hardware Description Language (VHDL) and field programmable gate arrays (FPGAs). Our system uses an automated GP engine, as opposed to a human designer, to evolve a hardware design composed of one or more FPGAs that will maximally achieve an application's software requirements. Several variants of our system exist; other variants are currently under development. The focus of this paper is to describe our original system design and its most recent revision to date.

When searching for a specific item of information across a vast number of databases accessible on the World Wide Web (WWW), one is faced with the problem of obtaining an intelligent response to a topic query in a feasible period of time. One such complicated grouping of information is the United States legal code where the typical query can bring back tens of thousands of related documents spanning numerous law repositories. To be practical, efficient information retrieval is critical, i.e., decisions must be made as to which databases to search and which of the information hits to return. One approach is to search the repositories in parallel using intelligent and adaptive mobile software agents. In this paper, we describe various tradeoffs and the feasibility of using adaptable mobile Java agents to solve the problem of efficiently searching and filtering through large amounts of information on the WWW. We show that for a legal code keyword query, mobile Java agents can be made to adapt (e.g., refocus their search criteria and reroute their search path) to efficiently retrieve the desired information within a new optimized search region of the WWW.

The focus of this paper is to present the results of our investigation and evaluation of various shared-memory parallelizations of the data association problem in multitarget tracking. The multitarget tracking algorithm developed was for a sparse air traffic surveillance problem, and is based on an Interacting Multiple Model (IMM) state estimator embedded into the (2D) assignment framework. The IMM estimator imposes a computational burden in terms of both space and time complexity, since more than one filter model is used to calculate state estimates, covariances, and likelihood functions. In fact, contrary to conventional wisdom, for sparse multitarget tracking problems, we show that the assignment (or data association) problem is not the major computational bottleneck. Instead, the interface to the assignment problem, namely, computing the rather numerous gating tests and IMM state estimates, covariance calculations, and likelihood function evaluations (used as cost coefficients in the assignment problem), is the major source of the workload. Using a measurement database based on two FAA air traffic control radars, we show that a "coarse-grained" (dynamic) parallelization across the numerous tracks found in a multitarget tracking problem is robust, scalable, and demonstrates superior computational performance to previously proposed "fine-grained" (static) parallelizations within the IMM.

We present a robust scalable parallelization of a multitarget tracking algorithm developed for air traffic surveillance. We couple the state estimation and data association problems by embedding an interacting multiple model (IMM) state estimator into an optimization-based assignment framework. A SPMD distributed-memory parallelization is described wherein the interface to the optimization problem, namely computing the rather numerous gating and IMM state estimates, covariance calculations, and likelihood function evaluations (used as cost coefficients in the assignment problem), is parallelized. We describe several heuristic algorithms developed for the inherent task allocation problem wherein the problem is one of assigning track tasks, having uncertain processing costs and negligible communication costs, across a set of homogeneous processors to minimize workload imbalances. Using a measurement database based on two FAA air traffic central radars, courtesy of Rome Laboratory, we show that near linear speedups are obtainable on a 32-node Intel Paragon supercomputer using simple task allocation algorithms.