Throughout its history, from the early four-circuit gate-array chips of the late 1960s to today's billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and high-performance product development. The combination of demanding designs and close cooperation among product, technology, and tool development has given rise to many innovations in the electronic design automation (EDA) area and provided IBM with a significant competitive advantage. This paper highlights IBM's contributions over the last four decades and presents a view of the future, where the best methods of multimillion gate ASIC and gigahertz microprocessor design are converged to enable highly productive system-on-a-chip designs that include widely diverse hardware and software components.

In this paper we compare different methods for calculating coupling noise, specially for use in the early design phase of a high performance custom design when all the detailed physical design information is not available. This analysis can be important in the design of functional blocks such as data paths in microprocessors, where if noise avoidance is included in the design planning phase, later changes in the design may be avoided. Thus, reducing the number of design iterations and overall design time. The ideal noise calculation technique should be very fast and reasonably accurate so as to account for all significant parameters that will affect the noise. We consider three different techniques and compare them with an exact analysis using a circuit simulator. It is shown that a lumped model is quite accurate for predicting noise on a variety of wire geometries up to 3 mm in length. We also propose a technique to extend this model to the practically important case when bus wires overlap only partially with neighbors.

In this paper, we describe a novel methodology for obtaining statistically-based worst case (i.e. 3-/spl sigma/) R (resistance), C (capacitance), and delay given variations in interconnect-related process parameters. Our approach is based on a weighted root-sum square method to derive 3-/spl sigma/ C. A Monte Carlo-based method is used for the generation of 3-/spl sigma/ R as well as randomized distributed RC nets to obtain realistic 3-/spl sigma/ delays for long interconnect nets such as global critical paths. Using this methodology for a long critical net analysis on a 0.35 /spl mu/m process, a more than 70% improvement in 3-/spl sigma/ delay estimation compared with the traditional skew-corner worst case delay can be realized.

In this paper we study the requirements for interconnect in deep-submicron technologies and identify critical factors that will require innovations in process technology, process integration and circuit-and-system design techniques. We also describe a scaling scheme for global lines to optimize the interconnect for a given application domain such as microprocessors, ASIC's or memory. For local interconnect we demonstrate that cross-talk is the major challenge which can be addressed by selectively using larger drivers to reduce cross-talk noise when necessary. An interconnect system optimization methodology is also presented that can be used to determine the geometry parameters of a multi-level interconnect system based on the criterion for performance and reliability.

This paper describes a Galerkin/spherical harmonics approach for solving the coupled Poisson-Boltzmann system of equations for the electron distribution function and the electric potential, which can then be used to calculate other parameters of interest such as current flow and electron temperature. The Galerkin approach described here has some pragmatic advantages in space-dependent problems over more commonly used term-matching techniques for arbitrary order spherical harmonic expansions in momentum space, but the method requires a careful treatment of the boundary conditions and upwinded discretization methods. Results are presented for nonuniformly doped one-dimensional devices using up to third order spherical harmonics to show the importance of including higher order harmonics to accurately calculate the distribution function in high field regions.

The authors develop a robust and efficient numerical solution of the hydrodynamic model, which solves the energy balance equation, and compare predictions of this model, using one set of parameters, with experimental nMOSFET characteristics for a range of channel lengths down to ultrashort channels. The substrate current is calculated by direct integration of the energy distribution function, which uses the computed temperature to obtain the number of high energy electrons. The drain current calculated using this method is accurate for a range of channel lengths and biases, and correctly predicts the observed enhanced transconductance for ultrashort-channel devices. The substrate current matches the experimental data for a range of channel lengths and biases above threshold with one set of physically reasonable parameters.>