Creator is a concurrent simulator for design verification and fault simulation of large circuits that highly integrates several traditional and innovative techniques. This is achieved by the introduction of a minimal information concept. Traditional techniques derived from previous works are Multiple List Traversal (MLT), trigger inhibition, fraternal event processing, list events, acid clock suppression, whereas the new ideas are function lists and evaluation functions, persistence time, positioning algorithm, evaluation triggering algorithm, combination of Single List Traversal (SLT) and MLT, and the implementation of transport delay in fault simulation. Generally the concurrent algorithm increases in complexity and the implementations grow in size and lose in performance as soon as higher abstraction levels are added beyond the gate one. To overcome this limitation, all the Creator's techniques are not related to a specific abstraction level and lead to an intrinsic multilevel concurrent fault simulator. Experimental results are reported to compare Creator with our previous simulator and the state-of-the-art commercial simulator Verifault-XL on several platforms.>

Article Free Access Share on Creator: General and efficient multilevel concurrent fault simulation Authors: P. L. Montessoro CENS/CNR, Politecnico di Torino, Torino, Italy CENS/CNR, Politecnico di Torino, Torino, ItalyView Profile , S. Gai Dip. di Automatica ed Informatica, Politecnico di Torino, Torino, Italy Dip. di Automatica ed Informatica, Politecnico di Torino, Torino, ItalyView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 160–163https://doi.org/10.1145/127601.127653Online:01 June 1991Publication History 12citation157DownloadsMetricsTotal Citations12Total Downloads157Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Accuracy, generality and efficiency are critical factors when fault simulation of VLSI circuits is the target. The concurrent algorithm is the only solution when generality and accuracy is required. Its differential representation of the network status saves memory and CPU time, but due to its complexity the implementations grow in size and lose in performance as soon as higher abstraction levels are added beyond the gate one. In the paper the minimal information concept is discussed, and its applications to the key algorithms for concurrent event-driven simulation are shown. New advanced generalized techniques for multiple list traversal (MLT), trigger inhibition, fraternal event processing, list events, edge sensitive inputs, compile-driven evaluation functions, functional fault sources and clock suppression are presented for the first time in a truly unified context.>

A technique that makes it possible to significantly improve the effectiveness of the differential algorithm for the fault simulation of synchronous sequential circuits is presented. The approach is based on dynamically reordering the fault list before the simulation of each input pattern: faults not yet detected are grouped according to a strategy aiming at minimizing the status differences between successive faults. In such a way the activity to be processed while computing each faulty circuit is minimized at a quite low computational cost. Experimental results are provided showing the effectiveness of the proposed method.>

The dynamic removal of faults before the end of the test pattern is reached, called fault dropping (FD), is considered. The conventional technique, called synchronous FD, is analyzed. An asynchronous FD method is introduced and its performance compared with that of the conventional method. It is based on the concept of removing descriptors while the simulation procedures access the data structure. This technique guarantees the maximum efficiency in reducing the computational effort. Experimental results show that it can considerably speed up simulation, particularly for large networks. It is shown that a mixed synchronous/asynchronous approach can optimize the total amount of memory needed.>

A technique, referred to as asynchronous fault dropping, is discussed. It is based on the concept of removing descriptors while the simulation procedures access the data structure. This technique guarantees the maximum efficiency in reducing the computational effort. Experimental results show that it can considerably speed up simulation, particularly for large networks. Lastly, consideration is given to the possibility of using a mixed approach in the light of the dynamic memory requirement during the initialization phase. It is shown that combination of synchronous and asynchronous fault dropping can optimize the total amount of memory needed.>

MOZART, a concurrent fault simulator for large circuits described at the register-transfer, functional, gate, and switch levels, is described. The requirements of multilevel simulation have guided the definition of MOZART's syntax, value set, delay model, and algorithms. Performance is improved by reducing unnecessary activity. Two such techniques are levelized: two-pass simulation, which minimizes the number of events and evaluations, and list event scheduling, which allows optimized processing of simultaneous (fraternal) events for concurrent machines. Moreover, efficient handling of abnormally large or active fault machines can improve fault-simulator performance by several orders of magnitude. These and related issues are discussed; both analytical and experimental evidence is provided for the effectiveness of the solutions adopted in MOZART. A performance metric is introduced for fault simulation, based on comparison with the serial algorithm, and is more accurate than those used in the past.>

This paper addresses the problem of event-directed logic simulation with part of the elements having zero delay. Incoherences arising from spikes having null duration (i.e., multiple transitions of a signal at a given simulation time, due to the simulation algorithm) are solved by a Two-Pass procedure, combining levelizing and event-driven simulation and yielding Ordered Activity Propagation. To overcome the speed degradation with respect to One-Pass simulation, a variation of the usual Two-Pass technique, termed Predictor/Corrector, is introduced at the gate level. Ordered Activity Propagation is also beneficial to concurrent multilevel simulation.

Fault simulation of circuits described at multiple levels of abstraction (RT, gate, switch) is a major problem in the area of CAD and testing. Although the concurrent paradigm is generally acknowledged as the most efficient, several techniques are crucial to successfully extend it to multilevel simulation of large circuits. In particular, based on multilist traversal, fraternal event processing, list events, and levelizing, advances are presented here in simulation speed, accuracy, and generality. For zero-delay elements, the simulation of irrelevant activity is avoided, but the accuracy of structural (interconnect) logic simulation is maintained. What is described here has been implemented in MOZART, and detailed experimental results are reported. Relative to the good machine, the average faulty machine is simulated 900 to 17 000 times faster. The approach presented is not restricted to fault simulation, and is thus applicable to the new area of concurrent case simulation.

When designing fault-tolerant systems including programmable logic arrays (PLAs), the various aspects of these circuits concerning fault diagnosis have to be taken into account. The peculiarity of these aspects, ranging from fault models to test generation algorithms and to self-checking structures, is due to the regularity of PLAs. The fault model generally accepted for PLAs is the crosspoint defect; it is employed by dedicated test generation algorithms, based on the fact that PLAs implement a two-level combinational function. The problem of accessing inputs and outputs of the PLA can be alleviated by augmenting the PLA itself so as to simplify the test vectors to be applied, making them function independent in the limit. A further step consists in the addition of the circuitry required to generate test vectors and to evaluate the answer, thus obtaining a built-in self-test (BIST) architecture. Finally, high reliability can be achieved with PLAs featuring concurrent error detection.

Abstract The paper discusses the problem of dynamic storage allocation (DSA) using C in a VMS environment. The problem is studied in a specific context, i.e. fault simulation of logic circuits. However, owing to its intrinsic generality, the adopted solution can be effectively applied to a large number of similar situations. It is shown how the use of standard C‐functions for dynamic memory allocation result unacceptable for efficiency reasons and different implementation strategies to solve the problem are presented.

The increasing complexity of VLSI systems demands structured approaches to reduce both design time and test generation effort. PLA's and scan paths have both been widely reported to be efficient in this sense. This correspondence presents an easily testable structure and its related testing strategies. The circuits are assumed to be based on the interconnection of combinatorial macros, mostly implemented by PLA's; tests are generated locally, considering the involved macro as an isolated item, and then are expressed in terms of primary inputs and outputs using a topological approach as general strategy and algebraic techniques for the propagation of signals through macros. Propagation is dealt with by new algorithms. Since the problem of test generation is NP-hard, a set of heuristics is introduced to keep the amount of computation reasonable; several implementation issues are finally investigated.

PART is a system for PLA testing and design verification, intended to be properly interfaced with other existing tools to generate a comprehensive design environment. To this purpose, it provides several facilities, among which the capability of generating a fault population on the basis of layout information. PART aims at producing a very compact test set for all detectable crosspoint defects, using limited amounts of run time and storage. This is achieved by means of an efficient partitioning algorithm together with powerful heuristics. Test minimality is ensured by a simple procedure. In the present paper these are discussed, experimental results are given and a comparison with competing strategies is made.