A 14-bit, 6.7 MS/s successive-approximation-register (SAR) A/D converter (ADC) is presented with on-chip autocalibration. An all-digital calibration algorithm with only two extra half-unit capacitors in capacitive DAC (CDAC) enables the ADC to correct itself from mismatch errors. We introduce digital heavy on-the-fly autocalibration, with novel reuse mechanism of existing capacitors, which deliver analog-precision error-correction yielding superior integral-nonlinearity (INL) and spurious free dynamic range (SFDR) at lowest area. The design is limited by thermal noise and not by mismatch error. A self-shut mechanism in dynamic comparator saves power consumption. A 0.018 mm2test chip in a 65-nm CMOS process consumes$98~\mu $W power. The calibration improves the INL of the ADC from >20 least significant bit (LSB) to${}_{W}$of 5.8 fJ/conv-step and FoM${}_{S}$of 175 dB at an area efficiency (AE) of$7.2~\mu $m2/code.

In this paper, we present the analysis and optimization method of energy efficiency in a Strong-Arm Latch-based dynamic comparator with additional capacitors to reduce input referred noise (IRN) for high accuracy ADC. Distributing the additional capacitors in integration and regeneration nodes with a specific ratio achieves the best energy efficiency. In the simulation, the comparator achieves an energy efficiency of 198fJ/comparison at an IRN of$165\mu \text{Vrms}$, delivering an overall Figure-of-Merit (FoM) of 5.39$\text{nJ}.\mu \mathrm{V}^{2}$. The comparator is designed and fabricated in a 65-nm CMOS process and integrated into a SAR ADC. The ADC's measured performance indicates that the comparator's performance is at par with simulated results.

In this work, a novel low-noise active pixel sensor (APS) is proposed which deploys in-pixel chopping and switched biasing to reduce the temporal noise. The source follower (SF) of an APS is the major contributor of the temporal noise. The proposed sensor is a modified conventional 3T pixel with an nwell/psub photodiode (PD) as photo-sensing element. To implement in-pixel chopping, two minimal sized additional nMOS switches are used per pixel. The switched biasing is implemented using two column-level (ps and ns) switches without affecting the pixel fill-factor (FF). The noise reduction techniques are validated through measured results obtained from a prototype sensor fabricated in 350 nm OPTO process from AMS. The sensor consists of a 2-D array of$128\times 128$pixels. The proposed pixel is designed with an area of$11\mu \mathrm{m}\times 11\mu \mathrm{m}$achieving a FF of 35%. A total noise reduction (and enhancement in dynamic range (DR)) of around 16 dB is achieved from in-pixel chopping with 8 MHz chopping frequency$(f_{\text{ch}})$and switched biasing.

An input folding cyclic ADC for column-parallel readout in CMOS image sensor is proposed. A double sampling circuit in the CMOS image sensor is reused to perform input folding operation in cyclic ADC. In addition, a push-pull configuration based slew rate enhancement technique is used to reduce the settling time of multiplying digital to analog converter. The ADC results in a conversion rate of 1.38 MS/s while consuming 560 $\mu$W of power. A prototype CMOS image sensor, with 12-bit column-parallel cyclic ADC, is designed and fabricated in AMS 350 nm CMOS OPTO process at 3.3 V power supply. For a $96\times 64$ pixel array, the row readout time of 720 ns is achieved, which is two to five times smaller compared to the state-of-the-art.

This work presents a low noise active pixel sensor. It uses one additional transistor compared to standard 4T pixel to obtain 1/f noise reduction and high conversion gain. 1/f noise is reduced by periodically switching the in-pixel source follower between depletion and inversion. The depletion state is achieved by re-configuring the source follower into a MOS capacitor and depleting the channel by controlling the source-drain terminal. The state change of the in-pixel source follower also enhances the conversion gain. The test chip has a 64 × 64 pixel array with a 10 μm pixel pitch fabricated in 350 nm AMS process. The measured integrated noise of a pixel in the frequency band 128 Hz to 50 KHz is 728 μVrmswithout switching. At a switching frequency of 4 MHz, the integrated noise reduces to 306 μVrmsafter switching resulting in a 7.5 dB reduction. The input referred noise is reduced from 26erms-to 7.3erms-after applying switching. When both, switching and conversion gain enhancement are applied, the input referred noise is further reduced to 2.3erms-with an enhanced conversion gain of 398 μV/e-.

A compressive acquisition technique for on-array image compression is proposed in this paper. It capitalizes on representation ability of accumulated spatial gradients of the acquired scene. The local variations inferred from strength of the accumulated gradients are used as cues to vary number of samples read through the image sensor readout. Such sampling enables the reconstruction using traditional interpolation techniques with desired quality. The proposed method is first verified using MATLAB simulations, where on an average, a compression of 87% is achieved, for a threshold of 40 intensity levels. The images are reconstructed using nearest neighbour interpolation (NNI) method which results in a mean peak signal to noise ratio (PSNR) value of 29.09 dB. The reconstructed images are further enhanced using deep convolutional neural network, which improves the PSNR to 32.46 dB. The biggest advantage of the proposed technique is low-complex hardware design. As a proof of concept, a hardware implementation of the technique is performed using discrete components. Pixel intensity values of standard images are converted into analog voltages using a data acquisition system and mapped in the input voltage range of 1.5 V -5.5 V. For a threshold of 3.8 V, the compression of 81% - 83% is observed for the considered images. The proposed technique is simple and effective, and is suitable for low-power complementary metal oxide semiconductor (CMOS) image sensors.

In this paper, a time-of-flight 3-D camera is presented for indoor/outdoor high-speed applications. A three-phase algorithm is proposed using one-tap/capacitor in-pixel background light subtraction. By integrating the background light only once, the standard four-phase time-of-flight operation is done in three-phases. The use of a single tap in the proposed pixel provides background light subtraction with lower mismatch and additionally, increases the camera speed. A 24 × 24 pixel array image sensor, fabricated in AMS 0.35-μm CMOS process is characterized in 2-D and 3-D mode for background light subtraction and distance estimation. The pixel pitch is 48 μm with 17.36% fill-factor. The sensor subtracts 125-klx background light with 8.2-cm distance offset at 80-cm object distance, without using an optical filter. The background-to-signal-ratio is 32.04 dB while frame rate of the camera is 207 and 100 fps in 2-D and 3-D mode, respectively.

This paper presents an accelerated-detection of regeneration in comparators using limited-output swing regenerative latch. The proposed method increases the operating clock frequency of fixed-current biased comparators without an increase in the static power consumption. The accelerated-detection comparator was fabricated in UMC 180 nm technology. The measurements show that the proposed technique increases the comparator-operating frequency more than twice and reduces the power consumption by 25% compared to similar circuits reported earlier. The comparisons are performed at a maximum clock frequency of 43 MHz while consuming 2.4 μW power from a supply of 1.8 V.

A 12-bit, programmable hybrid ADC for CMOS image sensor is proposed in this paper. The hybrid ADC internally uses cyclic-SAR architecture and results in an area efficient and high speed design. To minimize the total column ADC area, the elements of cyclic ADC are reused for SAR operation. The 12-bit programmable ADC can be operated either in high resolution mode or high speed mode depending on the number of bits allocated per stage. The prototype CMOS image sensor is designed and fabricated in AMS 350 nm CMOS OPTO process. A three-transistor pixel architecture followed by column parallel-readout circuit is implemented in a 9 μm column pitch. A prototype 128 × 96 image sensor consumes 62.7 mW of power at 3.3 V power supply.

A high dynamic range image sensor which uses a linear-logarithmic counting scheme to provide user programmable sensitivity variation for low light imaging application is presented. In a 3T pixel, if the photo-signal information is converted to time domain instead of voltage, the dynamic range for low light signals is no longer limited by sensor noise floor. However, it is still limited by the readout circuitry which is required to obtain digital bits for image acquisition. The proposed algorithm prevents the saturation of the readout circuitry by modifying the frequency of chip level counter so that it counts in a linear-logarithmic manner. The linear-logarithmic counter is integrated with the column circuitry and pixel in such a way that it enables low light photo-signal capture without losing the high light signal information. A chip with the proposed technique has been designed in 0.35 μm AMS OPTO process. The test chip has a 128 × 128, 3T pixel array with 9 μm pixel pitch. Simulation results show that maximum dynamic range obtained is 95 dB. The imager provides a user-programmable sensitivity curve depending upon the application. The extra hardware is added only at the chip level and no ramp generator is used, making the technique area and power efficient efficient.

This paper presents a technique to automatically adapt the bandwidth of the low-pass filter (LPF) of the phase interpolator (PI) used in bang-bang clock and data recovery (CDR) circuits. A technique for introducing the reference nonlinearity in the presence of PI's nonlinearity is presented. This reference is used for LPF bandwidth adaptation. A mathematical model for the PI nonlinearity and introduction of reference nonlinearity is proposed. Using this model, analysis and design of the proposed bandwidth adaptation are done. The technique is verified by simulations and Si-measurements using a full-rate bang-bang CDR, which is fabricated in 180-nm CMOS technology. The PI occupies an area of 0.014 mm2and consumes 1.1 mA for 1-GHz PI clock frequency while working on 1.8-V supply.

A 12-bit, 1.67-MS/s, two-stage cyclic ADC, using a 1.5-bit algorithm in a 2.5-bit framework is proposed in this brief. The number of accurate comparators is reduced to half as compared with the conventional 2.5-bit stage, which reduces the power consumption. Furthermore, the pipelined operation of the two stages reduces the total number of clock-cycles, which improves the conversion rate. The proposed ADC is designed and fabricated in a standard 180-nm CMOS technology. The obtained differential nonlinearity and integral nonlinearity are +0.5/-0.5 LSB and +0.8/-0.9 LSB, respectively. The ADC consumes 435-μW of power and occupies an area of 0.045 mm2. The postlayout simulations of ADC designed in a column-pitch of 5.6 μm show that it is suitable for column-parallel readout in CMOS image sensors.

Ultrasound (US) image despeckling is a problem of high clinical importance. Machine learning solutions to the problem are considered impractical due to the unavailability of speckle-free US image dataset. On the other hand, the classical approaches, which are able to provide the desired outputs, have limitations like input dependent parameter tuning. In this work, a convolutional neural network (CNN) is developed which learns to remove speckle from US images using the outputs of these classical approaches. It is observed that the existing approaches can be combined in a complementary manner to generate an output better than their individual outputs. Thus, the CNN is trained using the individual outputs as well as the output ensembles. It eliminates the cumbersome process of parameter tuning required by the existing approaches for every new input. Further, the proposed CNN is able to outperform the state-of-the-art despeckling approaches and produces the outputs even better than the ensembles for certain images.

Vascular region segmentation in ultrasound images is necessary for applications like automatic registration, and surgical navigation. In this paper, a pipelined network comprising of a convolutional neural network (CNN) followed by unsupervised clustering is proposed to perform vessel segmentation in liver ultrasound images. The work is motivated by the tremendous success of CNNs in object detection and localization. CNN here is trained to localize vascular regions, which are subsequently segmented by the clustering. The proposed network results in 99.14% pixel accuracy and 69.62% mean region intersection over union on 132 images. These values are better than some existing methods.

A 12-bit, 1 MS/s, two-stage cyclic ADC, with novel 2.5-bit/cycle architecture is proposed in this paper. A 1.5-bit algorithm is used in a 2.5-bit framework, which reduces the required number of accurate comparators and power consumption by 42%. Further, the ADC shows 46% improvement in the conversion rate as compared to the state-of-the-art two-stage cyclic ADC. The proposed ADC is designed and fabricated in a standard 180 nm CMOS technology. The obtained values of DNL and INL are +0.5/-0.5 LSB and +0.8/-0.9 LSB respectively. The ADC consumes 0.8 mW of power and occupies an area of 0.045 mm2with a FoM of 0.19 pJ/conversion-step. The proposed ADC when designed in a column pitch of 5.6 μm, will result in a frame-rate of 1000 frames/sec for a 1 Mpixel array.

On-chip presence of emerging nonvolatile resistive memory devices provide opportunities to perform different types of computing and storage operations with several advantages. A unique application of oxide based resistive memory (OxRAM) devices in CMOS Image Sensors (CIS) for improvement of pixel dynamic range (DR) is proposed in this paper. In CIS, DR signifies the detectable range of light intensity. A modified 3T-APS (Active Pixel Sensor) circuit that incorporates OxRAM in 1T-1R configuration is proposed for DR improvement in case of low exposure situations. We show relative pixel DR improvement through OxRAM resistive switching during exposure and study the impact of different preconditioning states. Best case, simulated relative pixel DR improvement of ~34 dB was obtained for the proposed design. To study the system level impact of the proposed pixel a simplified behavioral model based simulation of an array with 580 × 950 pixels was performed.

In this letter, we aim to develop a deep adversarial despeckling approach to enhance the quality of ultrasound images. Most of the existing approaches target a complete removal of speckle, which produces oversmooth outputs and results in loss of structural details. In contrast, the proposed approach reduces the speckle extent without altering the structural and qualitative attributes of the ultrasound images. A despeckling residual neural network (DRNN) is trained with an adversarial loss imposed by a discriminator. The discriminator tries to differentiate between the despeckled images generated by the DRNN and the set of high-quality images. Further to prevent the developed network from oversmoothing, a structural loss term is used along with the adversarial loss. Experimental evaluations show that the proposed DRNN outperforms the state-of-the-art despeckling approaches in terms of the structural similarity index measure, peak signal to noise ratio, edge preservation index, and speckle region's signal to noise ratio.

Anisotropic diffusion filters are one of the best choices for speckle reduction in the ultrasound images. These filters control the diffusion flux flow using local image statistics and provide the desired speckle suppression. However, inefficient use of edge characteristics results in either oversmooth image or an image containing misinterpreted spurious edges. As a result, the diagnostic quality of the images becomes a concern. To alleviate such problems, a novel anisotropic diffusion-based speckle reducing filter is proposed in this paper. A probability density function of the edges along with pixel relativity information is used to control the diffusion flux flow. The probability density function helps in removing the spurious edges and the pixel relativity reduces the oversmoothing effects. Furthermore, the filtering is performed in superpixel domain to reduce the execution time, wherein a minimum of 15% of the total number of image pixels can be used. For performance evaluation, 31 frames of three synthetic images and 40 real ultrasound images are used. In most of the experiments, the proposed filter shows a better performance as compared to the state-of-the-art filters in terms of the speckle region's signal-to-noise ratio and mean square error. It also shows a comparative performance for figure of merit and structural similarity measure index. Furthermore, in the subjective evaluation, performed by the expert radiologists, the proposed filter's outputs are preferred for the improved contrast and sharpness of the object boundaries. Hence, the proposed filtering framework is suitable to reduce the unwanted speckle and improve the quality of the ultrasound images.

This brief presents a technique for estimating the nonlinearity of phase interpolators (PIs) used in bang-bang phase detector-based clock and data recovery circuits. Using this estimation, the nonlinearity is compensated in a closed-loop manner. A Math model is proposed, which provides a theoretical basis for the nonlinearity estimation technique. The proposed technique is verified with the MATLAB model and with the Math model, which match within an LSB. The compensated nonlinearity lies within ±0.5 LSB of the PI for wide range of input conditions.

A low latency and a low power comparator is presented in this paper. The concept of current aiding at the output nodes of SR latch is proposed to enhance the switching speed of the comparator. The current flowing through the output nodes of regenerative latch is sensed and the amplified difference of these two currents is applied to the output nodes of SR latch. The circuit is designed and simulated in UMC 180 nm CMOS technology. Circuit consumes total power of 4.289 μW while operating at the clock frequency of 20 MHz. Measurement results proved that the designed comparator requires maximum of three clock cycles to perform switching for the input range 250-850 mV.

A CMOS image sensor with an integrated wire grid polarizer to sense the polarization of light is presented. The chip consists of an array of 128 by 128 pixels, it occupies an area of 5×4 mm2and it has been designed and fabricated in a CMOS 180nm process. Extinction ratio of 6.3 and 7.7 were achieved. The sensor is used to classify materials based on the degree of polarization and the transmitted intensity after specular reflection on the material surface. The variation in the transmitted intensity among dielectrics and metals was successfully demonstrated.