This paper proposes a method for tuning compilations to improve the size, execution time and reliability of the final application altogether. Our approach implements a genetic strategy with a multi-objective evolution that takes advantage of the NSGA-II algorithm for selecting the best compilations. Experiments show that reliability can be improved by efficiently exploring the compiler optimization options. As a consequence, our method enhances the application fault coverage from 3% to 6% and gets increments of MWTF from 15% to 45%.

The retina is a very complex neural structure, which contains many different types of neurons interconnected with great precision, enabling sophisticated conditioning and coding of the visual information before it is passed via the optic nerve to higher visual centers. The encoding of visual information is one of the basic questions in visual and computational neuroscience and is also of seminal importance in the field of visual prostheses. In this framework, it is essential to have artificial retina systems to be able to function in a way as similar as possible to the biological retinas. This paper proposes an automatic evolutionary multi-objective strategy based on the NSGA-II algorithm for tuning retina models. Four metrics were adopted for guiding the algorithm in the search of those parameters that best approximate a synthetic retinal model output with real electrophysiological recordings. Results show that this procedure exhibits a high flexibility when different trade-offs has to be considered during the design of customized neuro prostheses.

Integrity assurance of configuration data has a significant impact on microcontroller-based systems reliability. This is especially true when running applications driven by events which behavior is tightly coupled to this kind of data. This work proposes a new hybrid technique that combines hardware and software resources for detecting and recovering soft-errors in system configuration data. Our approach is based on the utilization of a common built-in microcontroller resource (timer) that works jointly with a software-based technique, which is responsible to periodically refresh the configuration data. The experiments demonstrate that non-destructive single event effects can be effectively mitigated with reduced overheads. Results show an important increase in fault coverage for SEUs and SETs, about one order of magnitude.

In this paper, a new approach to facilitate the development of heterogeneous embedded vision systems, by means of a software-friendly design flow is proposed. Our work is based on a framework called AMAZynq, especially focused on leverage the resources of Xilinx Zynq devices. Starting from an OpenCV code, the user defines explicitly the HW/SW partition and the AMAZynq produces the corresponding hardware and software infrastructures. The result is a SoC that not only matches the original functionality, but also accelerates it by means of an automatically generated and verified HLS core.

The protection of processor-based systems to mitigate the harmful effect of transient faults (soft errors) is gaining importance as technology shrinks. At the same time, for large segments of embedded markets, parameters like cost and performance continue to be as important as reliability. This paper presents a compiler-based methodology for facilitating the design of fault-tolerant embedded systems. The methodology is supported by an infrastructure that permits to easily combine hardware/software soft errors mitigation techniques in order to best satisfy both usual design constraints and dependability requirements. It is based on a generic microprocessor architecture that facilitates the implementation of software-based techniques, providing a uniform isolated-from-target hardening core that allows the automatic generation of protected source code (hardened code). Two case studies are presented. In the first one, several software-based mitigation techniques are implemented and evaluated showing the flexibility of the infrastructure. In the second one, a customized fault tolerant embedded system is designed by combining selective protection on both hardware and software. Several trade-offs among performance, code size, reliability, and hardware costs have been explored. Results show the applicability of the approach. Among the developed software-based mitigation techniques, a novel selective version of the well known SWIFT-R is presented.

Technological advances of Field Programmable Gate Array (FPGA) are making that this technology becomes the most preferred platform for the rapid prototyping of highly integrated digital systems. In addition, protection of processor-based systems to mitigate the harmful effects of radiation-induced upset events is gaining importance while technology shrinks. In this context, the main contribution of this work is a novel rapid prototyping approach for the co-design of dependable embedded systems using FPGA. This is supported by a hardening platform that allows combining software-only fault-tolerance techniques with hardware-only approaches, representing several trade-offs among design constraints, reliability and cost. As case study, several radiation-tolerant embedded systems have been developed based on a technology-independent version of the Picoblaze processor.

The protection of processor-based systems to mitigate the harmful effects of transient faults (hardening) is gaining importance as technology shrinks. Hybrid hardware/software hardening approaches are promising alternatives in the design of such fault tolerant systems. This paper presents a compiler-based infrastructure for facilitating the exploration of the design space between hardware-only and software-only fault tolerant techniques. The compiler design is based on a generic architecture that facilitates the implementation of software-based techniques, providing an uniform isolated-from-target hardening core. In this way, these methods can be implemented in an architecture independent way and can easily integrate new protection mechanisms to automatically produce hardened code. The infrastructure includes a simulator that provides information about memory and execution time overheads to aid the designer in the co-design decisions. The tool-chain is complemented by a hardware fault emulation tool that allows to measure the fault coverage of the different solutions running on the real system. A case study was implemented allowing to evaluate the flexibility of the infrastructure to fit the reliability requirements of the system within their memory and performance restrictions.

Tool path generation is one of the most complex problems in Computer Aided Manufacturing. The algorithm called Virtual Digitizing avoids this problem by its own definition but its computing cost is high. Presented in the paper there is a Virtual Digitizing hardware/software architecture that takes advantage of Field Programmable Gate Arrays (FPGAs) to improve the algorithm efficiency and to meet the current restrictions of the traditional no standard machines. In order to evaluate the architecture, a prototype was implemented using a commercial reconfigurable platform integrated within a numerically controlled lathe for shoe last machining. The performance of the system for tool path generation was measured for different trajectories and surface precisions using a database of real shoe models. The experiments show a significant speedup, keeping the computing error below the system tolerance.

This paper presents a synthesis tool for the automatic translation and optimization of bioinspired vision models into a FPL implementation. The software allows functional simulation and high level specification of the model, and produces a data-flow model using VHDL, which is synthesizable with different lower-level synthesis tools and for various FPGA technologies. The proposed design platform extends the features of the codesign environment CodeSimulink for implementing visual processing systems, starting from purely functional specifications. An optimization strategy based on the calculation of the Pareto front is also introduced to perform a multi-objective minimization of both, the circuit area and the root mean square of the computation error. Performance measurements for the FPL implementation of an example retina-like vision model on a FPGA-based PCI board are provided