A delay-locked loop (DLL) circuit is indispensable for clock synchronization in a chip incorporating several heterogeneous dice. It has been shown previously that a fault and soft-error-tolerant DLL can be achieved by triple-module redundancy (TMR) enhanced with a timing correction scheme. However, the prior work still has a severe limitation—it does not consider the latency of the clock tree, and this limitation will make it infeasible in realistic situations. We demonstrate in this article that this limitation can be overcome by a new “clock-latency-aware” architecture, thereby making a fault and soft-error-tolerant DLL truly realistic.

Time-to-digital converters (TDCs) are commonly used for on-chip instrumentation. This article proposes a low-cost Cyclic-TDC with several distinct features. It can adapt to the process variation to maintain a fine resolution across all process corners. This is made possible by a so-called one-way varactor cell (OWVC) and an autonomous calibration process. In addition, it supports easy process migration. Last but not least, we show how it can be used for clock jitter measurement with reduced output uncertainty. Simulation results using a 90-nm CMOS process and a 40-nm CMOS process are used to demonstrate their advantages.