Glass interposers have become a compelling option for 2.5-D heterogeneous integration compared to silicon. It allows 3-D stacking configuration between the embedded dies and the conventional flip-chip dies mounted directly on top at low cost. Furthermore, the interconnect pitch and through-glass-via (TGV) diameter in glass are becoming comparable to their counterparts in silicon. In this study, we investigate the power, performance, area (PPA), signal integrity (SI) and power integrity (PI) advantages of 3-D stacking afforded by glass interposers over silicon interposers. Our research employs a chiplet/package co-design approach, progressing from an register-transfer-level description of RISC-V chiplets to final graphic data system (GDS) layouts, utilizing TSMC 28 nm for chiplets and Georgia Tech’s 3-D glass packaging for the interposer. Compared to silicon, glass interposers offer a$2.6\times $reduction in area, a$21\times $reduction in wire length, a 17.72% reduction in full-chip power consumption, a 64.7% increase in SI and a$10\times $improvement in PI, with a 35% increase in thermal. Furthermore, we provide a detailed comparative analysis with 3-D Silicon technologies. It not only highlights the competitive advantages of glass interposers, but also provides critical insights into each design’s potential limitations and optimization opportunities.

Glass interposers enable 3D stacking between the chiplets embedded into the substrate and the ones stacked directly on top, which is not possible in silicon. In this work, we demonstrate the benefits of such stacking in glass interposers over silicon in terms of key system-level metrics including area, wirelength, signal, power, and thermal integrity. We achieve this goal with GDS layouts of both chiplets and interposers and sign-off simulations. Our experiments show that glass offers 2.6X area, 21X wirelength, 17.72% full-chip power, 64.7% signal integrity, and 10X power integrity improvement over silicon at the cost of 15% increase in temperature.