A significant number of contributions focusing on approximation techniques for Application Specific Integrated Circuits (ASIC) has become part of the scientific literature. Conversely, Field Programmable Gate Arrays (FPGAs) are often overlooked, despite their increasing spread. ASIC-based techniques are, however, often unsuitable when it comes to FPGA, providing little or no advantages at all, due to the inherent differences in the two target technologies. Most of the FPGA-based approximation techniques being recently proposed either rely on manual approximation, or are too tightly coupled with a particular FPGA fabric, making them ineffective or even inapplicable to other devices. Furthermore, they rely on machine-learning based predictors to drive the Design Space Exploration (DSE), that, given the high fidelity required, are usually burdensome to achieve, or even unfeasible when little or no training data is available. In this paper, we discuss a fabricand workload-independent approach to design power-optimized approximate circuits for FPGA. We exploit the existing bond between Look-Up Table (LUT)-mapping in FPGA synthesis and cut-enumeration in And-Inverter graph representation of digital circuits, and we resort to an analytical model to estimate the power consumption during the DSE, avoiding costly synthesis as well as machine-learning based predictors for hardware resources during the DSE. Several benchmark circuits are considered for evaluation purposes, and the significant savings achieved allow us to claim our approach is suitable for addressing approximate circuit design while targeting the FPGA.

Due to their run-time reconfigurability, short time-to-market, and lower prototype costs, FPGAs have become increasingly popular since their introduction. They found use in a wide variety of applications, including high-performance computing. However, when compared to ASICs, FPGAs offer lower performance, and they are power-hungry devices with low energy-efficiency. The emergence of Approximate Computing (AxC) represents a significant advancement in terms of enabling technology when applied to FPGA-based computing platforms. It has been effectively exploited in several application fields, achieving significant savings in energy and latency through a selective degradation of the output quality. Nevertheless, a generalized and systematic methodology for FPGA-based circuit design is still lacking. Indeed, most of the methods target ASIC-based systems, and, consequently, they offer minimal advantages or even an increase in resources when synthesized for FPGAs due to the architectural differences between the technologies. In this paper, we attempt to address this shortcoming by introducing our method for designing combinational logic circuits. It is based on and-inverter graph rewriting and multi-objective optimization, aiming for optimal trade-offs between quality of results and hardware overhead. Extensive experimental campaigns empirically prove that both generic logic and arithmetic circuits benefit from this approach.

Although the Automatic Train Operation (ATO) is consolidated in urban railways, its use on mainlines is still unexplored. Currently, the first prototypes of train with ATO capable of running on mainlines equipped with specific control systems (e.g., ETCS/ERTMS in Europe) have been realized. However, they require the active presence of staff on board. Recent research in innovative solutions for railway efficiency has opened to the possibility of extending the ATO concept to the Unattended Train Operation (UTO), i.e., the full automation of infrastructures and vehicles. In this context, a project based on synergistic collaboration between academia and the national railway industry has led to the definition of a new Vital Control module (VC). VC includes a PCB, managed by a reliable and safe hard Real-Time Operating System (RTOS). The hardware consists of a Eurocard-sized PCB that houses an Ultrazed-EG System on Module as computing core and embeds several communication interfaces to favor the inclusion in existing apparatus. The VC RTOS runs an application logic that acts as a real-time control core for the assessment of the on-cabin equipment operativity. VC is also responsible for detecting UTO-related hazardous situations by intervening with emergency braking. Both VC hardware and software are developed to be compliant with related safety standards. The proposed VC has been included in an automatic testbed to recreate real-time hazardous scenarios. In this context, VC system has proven to be able to mitigate these scenarios ~2 times faster than current ATO protection system.

Abstract Recent advances in technology and railway have led to the introduction of systems and infrastructures capable of driving trains automatically. The Automatic Train Operation (ATO) system has been optimized for active human supervision. The next challenge is to realize ATO systems capable of achieving unsupervised operations on the mainlines. However, at this aim, additional safety functionalities should be provided. In this paper, we propose a pioneer hardware/software Vital Control Module (VCM) architecture capable of expanding the control capabilities of the existing train control system. The VCM includes a Printed Circuit Board (PCB), to be integrated into the cabin equipment, managed by a reliable and safe hard Real-Time Operating System (RTOS). Both hardware and software are developed to be compliant with related safety standards. The VCM integrates an application logic that acts as an on-board equipment control core, assessing the overall operativity in real-time, and promptly issuing emergency brakes if hazardous situations occur. The application logic has been developed with a model-based approach via Simulink/Stateflow tool and implemented as a C-script on the Xilinx Ultrascale + core housed on the PCB. We have used two testbeds to evaluate the VCM performance. Experimental results showed that the Worst-Case Response Time (WCRT) by the application logic is 13.6 times smaller than the most limiting specification-related deadline. The achieved earliness (− 1.8 ms out of 2 ms of deadline) allows for the easy expansion of VCM’s train protection capabilities in the future. Results from the second testbed showed that the VCM can intervene to mitigate hazardous situations ~ 2 times faster than the current automatic train protection systems according to the related standard.