With the increasing integration of renewable energy devices, modern power systems have become complex, exhibiting diverse circuit topologies. Existing FPGA-based accelerators are optimized for fast single-topology simulation but lack the flexibility to handle multiple topology simulations. This paper proposes a scalable heterogeneous CPU-FPGA system designed for efficient simulation of diverse power system topologies. The proposed system enables real-time simulation for variable-scale power systems, distinguishing itself from conventional simulators by leveraging flexible matrix decomposition and a topology-aware approach. Our design specifically achieves the minimal latency of 100ns for both the boost and three-phase voltage source converter (VSC) models, highlighting its superior performance across diverse topologies. Introduced by dynamic fixed-point quantization, our proposal reduces 30.8% LUTs, 26.8% FFs, 22.2% BRAMs and 43.8% DSPs versus a fixed-point implementation with the same computational accuracy.

Quantum networks are at the forefront of next-generation communication technologies, providing unparalleled security by leveraging the fundamental properties of quantum mechanics. However, noise and interference adversely affect information sharing within quantum networks, causing quantum bit errors and diminishing the quality of quantum keys. To address this issue, high-speed quantum information error correction is necessitated and this work proposes an FPGA-accelerated error correction system based on low-density parity check (LDPC), incorporating algorithm-hardware co-optimizations. The proposed hardware architecture is applicable to generic LDPC soft decision algorithms and can adaptively select LDPC matrices with different code rates based on the quantum bit error rates. Experiment results demonstrate that the system exhibits high performance in error correction acceleration, achieving a throughput of 728 Mbps and up-to 9.4× speedup compared to existing FPGA-based LDPC error correction implementations.

Stochastic gradient descent has been a widely used machine learning algorithm, and interest in low-precision SGD is growing because it improves throughput and keeps efficient convergence. We propose MSDF-SGD, a novel approach allowing SGD to support arbitrary-precision training on FPGAs by employing most-significant digit-first arithmetic. MSDF-SGD is the first architecture that supports arbitrary-precision data, models, and intermediates at the same time. MSDF-SGD is evaluated via training linear classifiers on representative datasets. MSDF-SGD delivers a 1.6× speedup over state-of-the-art low-precision hardware implementations and converges up to 8.6× faster than cutting-edge implementations on CPUs. Finally, we provide a programming interface that permits building a custom arbitrary-precision training accelerator, making MSDF-SGD support more complicated, multi-layered and nonlinear models.