Machine Learning (ML) models are increasingly adopted in Cyber-Physical Systems (CPS), yet monolithic architectures hinder interpretability, verification, and safety assurance. By decomposing a CPS into modular sub-models and embedding formally defined safety policies during training, we can construct systems that are correct-by-construction rather than relying on post-hoc falsification or unscalable static verification.

Cryogenic power electronics has the potential to significantly improve Cyber Physical Systems (CPS) applications in aviation and space. However, their safety and reliability are yet to be studied systematically. To this end, we propose the first prototype of a deterministic toolchain for the design of Cryogenic Cyber Physical Systems (CCPS). Obviously, the design, verification and safety analysis of such systems pose considerable unknowns and challenges. Towards a potential solution, we propose an approach for unified functional safety, inspired by our earlier work. We leverage the recently developed deterministic framework (proposed by Google), called Logical Synchrony Networks, for distributed systems. This simplifies the modelling and safety analysis. Moreover, we propose a novel variant of Signal Temporal Logic (STL), called Synchronous Signal Temporal Logic (SSTL), which is specially tailored for CPS applications and designed using logical synchrony. We demonstrate the first prototype solution in the simulation of a CCPS system as a proof of concept.

Real-time CPSs using Artificial Neural Networks (ANNs) are traditionally developed as monolithic black-boxes. This results in designs that are often difficult to formally verify against safety specifications and implement on hardware for formal timing analysis. Consequently, their implementation as a composition of smaller ANNs has received recent interest. These are easier to implement, parallelise and validate. Despite this, the question of how to produce hardware-implementable compositional designs from existing monolithic ones remains largely unanswered. This work develops a novel procedure to replace large ANN monolithic designs with smaller compositional designs and implement them on a Field Programmable Gate Array (FPGA) for timing analysis using synchronous compositional semantics. To illustrate our approach, we develop regression and classification ANN designs for multiple real-life datasets. Using various design and model architecture variations, we show that using a compositional design instead of a monolithic design can achieve an $\mathbf{8 5 \%}$ reduction in WCET, around a $\mathbf{53 \%}$ reduction in hardware resources and around a 40% reduction in computations and neuron connections for a minor reduction in performance.