Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Matthew Giordano

dblp:342/8046 · DBLP profile ↗
← Back
3ranked-venue papers
0as first author
3since 2021 · last 2025
0000-0003-4351-7109ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Reconfigurable computing and FPGAs · 68% Memory systems · 32%
Computer networks
1 paper
Internet architecture and protocols · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Internet architecture and protocols › network architecture design › layered architecture › protocol layering
network stack
0.812024
Beehive: A Flexible Network Stack for Direct-Attached Accelerators · MICRO 2024
Reconfigurable computing and FPGAs
FPGA virtualization
0.712023
Reconfigurable Virtual Memory for FPGA-Driven I/O · ASPLOS (3) 2023
Memory systems › memory management
virtual memory
0.712023
Reconfigurable Virtual Memory for FPGA-Driven I/O · ASPLOS (3) 2023

Methods — techniques the papers use, named apart from their topics

network-on-chip · 1.5modular tiles · 1.5deadlock safety · 1.5
YearPublicationVenuePosition
2025 Apiary: An OS for the Modern FPGA
abstract
Many datacenter operators have deployed FPGAs as hardware accelerators because their reconfigurability allows them to be repurposed as the application mix changes. Directly attaching the FPGA to the network further reduces latency, improves cost-performance, and reduces energy use relative to mediating network communications with CPUs. However, building accelerated applications or services for direct-attached FPGAs is challenging, especially with the complex I/O and multi-accelerator capacity of modern FPGAs. To address this, we propose Apiary, a microkernel operating system for direct-attached FPGA accelerators. The key idea in Apiary is to raise the level of abstraction for accelerated application code, with security, virtualization, threaded execution, and interprocess communication provided by the hardware OS layer.
Katie Lim, Matthew Giordano, Irene Zhang, Baris Kasikci, Thomas E. Anderson
HotOS2
2024 Beehive: A Flexible Network Stack for Direct-Attached Accelerators
abstract
Direct-attached accelerators, where application accelerators are directly connected to the datacenter network via a hardware network stack, offer substantial benefits in terms of reduced latency, CPU overhead, and energy use. However, a key challenge is that modern datacenter network stacks are complex, with interleaved protocol layers, network management functions, and virtualization support. To operators, network feature agility, diagnostics, and manageability are often considered just as important as raw performance. By contrast, existing hardware network stacks only support basic protocols and are often difficult to extend since they use fixed processing pipelines. We propose Beehive, a new, open-source FPGA network stack for direct-attached accelerators designed to enable flexible and adaptive construction of complex network functionality in hardware. Application and network protocol elements are modularized as tiles over a network-on-chip substrate. Elements can be added or scaled up/down to match workload characteristics with minimal effort or changes to other elements. Flexible diagnostics and control are integral, with tooling to ensure deadlock safety. Our implementation interoperates with standard Linux TCP and UDP clients, with a 4x improvement in end-to-end RPC tail latency for Linux UDP clients versus a CPU-attached accelerator. Beehive is available at https://github:com/beehive-fpga/beehive
Katie Lim, Matthew Giordano, Theano Stavrinos, Irene Zhang, Jacob Nelson 0001, Baris Kasikci, Thomas E. Anderson
MICRO2
2023 Reconfigurable Virtual Memory for FPGA-Driven I/O
abstract
FPGAs are increasingly used to accelerate modern applications, and cloud providers offer FPGA platforms on-demand with a variety of FPGAs, I/O peripherals, and memory options. FPGA vendors expose I/O with low-level interfaces that limit application portability. Current approaches to abstracting these interfaces trade level of abstraction against performance.
Joshua Landgraf, Matthew Giordano, Esther Yoon, Christopher J. Rossbach
ASPLOS (3)2