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Demo Data from EDBT 2026 / reviewers in the wild / expert

Archille Montanaro

dblp:343/4689 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1999
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 1 heaviest of 1, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › system-level design
hardware design reuse		 0.011999
FPGA Design Experiences Using the CSELT VIP (TM) Library · FPGA 1999
YearPublicationVenuePosition
1999 FPGA Design Experiences Using the CSELT VIP (TM) Library
abstract
No abstract available.
Enrica Filippi, Archille Montanaro, Maurizio Paolini, Maura Turolla
 FPGA2