Dynamic Vision Sensors (DVS) are well suited for latency- and power-sensitive applications such as embodied intelligence and autonomous driving, owing to their event-driven operation and high spatiotemporal efficiency. However, under camera motion or low-light conditions, DVS frequently produces redundant or noisy events, compromising data sparsity and reliability. To address this challenge, we propose LiteDVS, a DVS architecture with region-aware hybrid readout and in-pixel denoising. LiteDVS integrates event streams for regions of interest with event frames for background areas, significantly reducing data redundancy. Furthermore, a lightweight in-pixel filter compatible with both readout modes is designed to suppress noise events with negligible latency overhead. Simulations in a SMIC 55 nm logic CMOS process demonstrate that LiteDVS achieves accurate denoising with energy consumptions of 317 fJ/event in stream mode and 41.8 fJ/event in frame mode.

Migrating a validated analog layout across technology nodes remains labor-intensive. Recent automatic migration methods often miss multi-level design intent embedded in expert layouts and may suffer from routing-induced LVS violations and unstable placement behaviors. We present GRAIN, a design-intent-driven analog layout migration framework that performs constraint-aware hierarchical placement migration to preserve multi-level placement behaviors, and uses guide-based routing that decouples similarity from legality via a maze router to reliably produce LVS-clean layouts. Experiments on real designs migrated from 65 nm to 40 nm and 28 nm show that, compared to a recent representative analog layout migration framework, GRAIN delivers 100% LVS-clean layouts without manual fixes and reduces area and wirelength by 13.8% and 29.2% on average, while also yielding post-layout metrics closer to the schematic.

Analog layout design heavily involves interactive processes between humans and design tools. electronic design automation (EDA) tools for this task are usually designed to use scripting commands or visualized buttons for manipulation, especially for interactive automation functionalities, which have a steep learning curve and cumbersome user experience, making a notable barrier to designers’ adoption. Aiming to address such a usability issue, this article introduces LayoutCopilot, a pioneering multiagent collaborative framework powered by large language models (LLMs) for interactive analog layout design. LayoutCopilot simplifies human-tool interaction by converting natural language instructions into executable script commands, and it interprets high-level design intents into actionable suggestions, significantly streamlining the design process. Experimental results demonstrate the flexibility, efficiency, and accessibility of LayoutCopilot in handling real-world analog designs.

With the CMOS technology advancing and the complexity of circuits growing, the demand for analog/mixed-signal design automation tools is increasing quickly. Although some tools have been developed to tackle this challenge, the performance degradation caused by process, voltage, and temperature (PVT) variations has been less considered. This paper presents PVTSizing, an optimization framework for PVT-robust analog circuit synthesis. PVTSizing adopts trust region Bayesian optimization (TuRBO) for high-quality initial datasets and reference points. Multi-task reinforcement learning (RL) is utilized for PVT optimization. Both TuRBO and RL are batch-friendly, allowing parallel sampling of design solutions. Meanwhile, critic-assisted pruning and zoom target metrics are proposed to improve sample efficiency and reduce runtime. In addition, this framework naturally supports sizing over random mismatch. On 4 real-world circuits with TSMC 28/180nm process, PVTSizing achieves 1.9X --8.8X sample efficiency and 1.6X --9.8X time efficiency improvements compared to prior sizing tools from both industry and academia.