Demo Data from EDBT 2026 / reviewers in the wild / expert
Shupei Fan
dblp:343/5932
· DBLP profile ↗
3ranked-venue papers
0as first author
3since 2021 · last 2026
0009-0004-5314-3002ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Processor architecture and microarchitecture · 62% Hardware accelerators and domain-specific architectures · 38% | |
| Artificial intelligence
1 paper |
Efficient and distributed learning · 100% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures
approximate computing accelerator |
0.9 | 1 | 2025 | SASDenSebLE: A Compact Vision Transformer Inference Architecture With Saturation-Approximate Softmax Dataflow Enabling Sequence-Parallelism Boosted Layer-Fusion Execution · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Processor architecture and microarchitecture
instruction set architecture |
0.9 | 1 | 2025 | Titan-I: An Open-Source, High Performance RISC-V Vector Core · MICRO 2025 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.9 | 1 | 2025 | SASDenSebLE: A Compact Vision Transformer Inference Architecture With Saturation-Approximate Softmax Dataflow Enabling Sequence-Parallelism Boosted Layer-Fusion Execution · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Processor architecture and microarchitecture
out-of-order execution |
0.9 | 1 | 2025 | Titan-I: An Open-Source, High Performance RISC-V Vector Core · MICRO 2025 |
Processor architecture and microarchitecture › instruction set architecture › vector extension
RISC-V vector extension |
0.9 | 1 | 2025 | Titan-I: An Open-Source, High Performance RISC-V Vector Core · MICRO 2025 |
Machine learning › Efficient and distributed learning › model merging
layer merging |
0.3 | 1 | 2025 | SASDenSebLE: A Compact Vision Transformer Inference Architecture With Saturation-Approximate Softmax Dataflow Enabling Sequence-Parallelism Boosted Layer-Fusion Execution · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Machine learning › Efficient and distributed learning
model inference |
0.3 | 1 | 2025 | SASDenSebLE: A Compact Vision Transformer Inference Architecture With Saturation-Approximate Softmax Dataflow Enabling Sequence-Parallelism Boosted Layer-Fusion Execution · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Processor architecture and microarchitecture
vector processing |
0.3 | 1 | 2025 | Titan-I: An Open-Source, High Performance RISC-V Vector Core · MICRO 2025 |
Methods — techniques the papers use, named apart from their topics
sequence parallelism · 1.7saturation approximation · 1.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | HybridSpec: Exploiting Hybrid-Bonding Memory to Accelerate LLM Serving Through Heterogeneous Architecture and Speculative Decoding
Zongle Huang, Wenbin Jia, Yaolei Li, Xinyuan Lin, Shupei Fan, Shuwen Deng, Yongpan Liu |
ISCA | 5 |
| 2025 | Titan-I: An Open-Source, High Performance RISC-V Vector CoreabstractVector processing has evolved from early systems like the CDC STAR-100 and Cray-1 to modern ISAs like ARM's Scalable Vector Extension (SVE) and RISC-V Vector (RVV) extensions.However, scaling vector processing for contemporary workloads presents challenges due to overheads in traditional architectures.We introduce Titan-I (T1), an out-of-order (OoO) RVV architecture designed Jiuyang Liu, Qinjun Li, Yunqian Luo, Jiongjia Lu, Shupei Fan, Jianhao Ye, Yanqi Yang, Zewen Ye, Yuhang Zeng, Wei Cong, Xuecheng Zou, Mingyu Gao 0001 |
MICRO | 6 |
| 2025 | SASDenSebLE: A Compact Vision Transformer Inference Architecture With Saturation-Approximate Softmax Dataflow Enabling Sequence-Parallelism Boosted Layer-Fusion Execution
Zongle Huang, Shupei Fan, Luchang Lei, Huazhong Yang, Yongpan Liu, Hongyang Jia |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 4 |