Recent advancements in artificial intelligence have led to the widespread use of convolutional neural networks (CNNs) in various fields. To improve hardware performance, numerous hardware accelerator circuits have been developed. However, the extensive use of processing elements (PEs) in these accelerators raises potential reliability concerns. Traditional modular redundancy techniques, while effective in error mitigation, come with substantial hardware costs. In this study, we introduce a cost-effective scheme designed for efficient on-line error detection and mitigation in CNNs. This scheme is based on innovative designs of approximate PEs. Specifically, we propose two potential designs for these approximate PEs and evaluate their cost-effectiveness. These approximate PEs, used in conjunction with the original PEs, form an Approximate Dual PE Redundancy (ADPR) and Approximate Triple PE Redundancy (ATPR) structure, which is essential for verifying the quality of PE computations. Additionally, we propose a novel error mitigation technique derived from our ADPR and ATPR structure, significantly enhancing the error tolerance of PEs. Notably, our approximate PE designs require only 64% of the area compared with previous designs, while maintaining similar levels of approximation errors.

Systolic-array AI accelerators operating near threshold voltage face significant timing reliability challenges due to increased PVT sensitivity. While Razor flip-flops offer accurate bit-level detection, their area overhead limits scalability. Existing timing monitors are more efficient but lack granularity and adaptability. This work presents a frontier-aligned timing monitor that enables low-overhead, bit-level visibility. By analyzing post-layout delays in a 7nm systolic array, we identify a MAC unit highly correlated with the global bit-wise delay frontier. A co-located monitor path with tunable delay buffers enables PVT-aware calibration and precise alignment. Experimental results show an average delay error of 3.1% and area overhead as low as 0.1% in large arrays. The proposed design supports scalable, energy-efficient runtime approximation and adaptive voltage/frequency scaling (AVFS), offering a practical solution for fine-grained timing management in modern AI accelerators.

In a Deep Neural Network (DNN) computing platform, memory is an essential component. Unfortunately, memory errors may occur due to various factors. The memory error rate may even increase significantly when low-power technologies are used. Therefore, it is crucial to cost-effectively protect memory against errors. However, most previous memory protection work for DNN has limited capability to deal with the case of high memory error rate. In this work, we first conduct a detailed study on the inherent error-tolerability of a DNN for memory errors with various error rates. The YOLOv4 DNN model is employed as a case study, and various memory error models are considered. In particular, we also investigate the effectiveness limitation of the previous error mitigation methods. Based on these analyses, we propose a novel protection method where memory errors with high error rate can be tolerated. The experimental results show that our method can guarantee only 1% DNN accuracy degradation even when the error rate is as high as 0.1%, which is a breakthrough in the literature. Moreover, the cost overhead of our method is still comparable to previous methods.

With the rapid development of machine learning technologies, more and more practical applications arise. Representative machine learning techniques that receive much attention include object detection and image classification, which can be applied to many applications, such as self-driving cars, traffic flow calculation, and detection of product defects in factories. In this article, we investigate tolerability of errors for input images in machine learning systems and develop a generic reliability enhancement methodology. This work is based on our preliminary studies on image classification, but we put major focuses in object detection applications and the comprehensive comparisons to the prior studies. The first one error-tolerability test method to support reliability enhancement of object detection applications is then proposed based on careful error-tolerability examination of input images. The experimental results show that the test accuracy of this method can achieve 93.06%, which is the state-of-the-art. One special advantage of the proposed method is that unlike the previous error-tolerance methods in the literature, no golden reference data are required for acceptability determination by the proposed method. Hence, on-line testing can be supported. Our method is also implemented and validated in hardware. The results show that the hardware performance is up to 192 frames per second (FPS), which can thus also support real-time operations.