The zero-crossing-based integrator (ZCBI) offers an energy-efficient alternative to traditional operational transconductance amplifier (OTA)-based switched-capacitor (SC) integrators in analog-to-digital converters (ADCs) such as Delta-Sigma (ΔΣ) and pipeline ADCs, particularly in low supply voltage scenarios. To achieve zero-crossing detection, the ZCBI requires a preset operation to set the output to supply voltage at the start of the integration phase. This preset operation consumes extra dynamic power in each integration phase, and limits the speed and dynamic range of the integrator. This paper introduces a new ZCBI that can determine the direction of zero crossing by a pre-judgement circuit, hence circumventing the need for the preset phase and supporting continuous two-way integration. As a proof of concept, a self-timed incremental zoom ADC using the proposed ZCBI has been fabricated in a standard 180-nm CMOS technology. This ADC consists of a coarse 5-bit SAR ADC and a fine second-order single-bit ΔΣ modulator. The ADC consumes 150 μW from a 1.8-V supply. An SNDR of 77.4 dB is achieved in a 6.25 kHz bandwidth, leading to a Schreier FoM of 154 dB. It is foreseen that implementations in a more advanced technology will further enhance the energy efficiency of the proposed design.

This paper presents an energy-efficient hybrid analog-to-digital converter (ADC) that combines a 5-bit successive approximation register (SAR) ADC for coarse conversion and a 6.5-bit analog-slope ADC for fine conversion. Benefiting from input range scaling by coarse SAR ADC, the linearity of the analog-slope ADC is significantly improved. The switching energy to drive the digital-to-analog converter (DAC) is minimized because the analog-slope ADC reuses the capacitor array of SAR ADC without additional capacitors to generate ramp. The ADC is implemented in 180 nm CMOS technology. At a sampling rate of 1 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 67.51 dB and a spurious-free dynamic range (SFDR) of 74.13 dB, particularly when the input approaches the Nyquist frequency, while consuming 137.8 µW from a 1.8 V supply. The resulting Walden and Schreier figures of merit are 72.30 fJ/conversion-step and 163.03 dB, respectively.

This paper presents a delay element with self-shutoff logic and delay range extension. The proposed delay element exhibits significant advantages in terms of energy consumption and delay range. The self-closing logic efficiently conserves energy by automatically interrupting the discharge path of delay capacitors once positive feedback is established. Furthermore, the self-shutoff logic is capable of delivering a sharp digital output. The delay extension scheme enables a significantly increased delay output with acceptable hardware overhead and power consumption. The tuning range of this work is 1.18 ns - 1.22 µs. The energy per delay of the proposed delay element in this paper is only 33.21 fJ, which represents a 33% reduction compared to the currently published delay element.

Level shifters are essential in ultra-low-power analog mixed-signal systems. This brief introduces a level shifter with auto-switch logic. The auto switch logic can automatically alter the connection mode of the pull-up network during transition phases. This approach allows the level shifter, when employing the current limiter, to preserve its strong pull-down capabilities while selecting the optimal path for cutting off the pull-up transistor. Additionally, other optimization strategies, such as pass transistors and a split inverter, are employed in this paper. The proposed level shifter is designed and simulated using a 65 nm multi-threshold CMOS process. In the 0.3 V to 1.2 V level conversion with a 1 MHz input frequency, the delay of the proposed level shifter is 5.80 ns, the energy per transition is 22.77 fJ, and the leakage power is 1.02 nW. When the input signal is relaxed to 1 KHz, the proposed level shifter achieves a minimum voltage of 140 mV.