The parallel operation technology plays a pivotal role in enhancing performance of 3-D nand flash-based SSDs. High-parallel distribution of consecutive pages places the pages on different parallel units, thereby improving the parallelism and throughput of read requests. However, the high-parallel distribution generates two problems: 1) aggravating data fragmentation and 2) exacerbating the impact of garbage collection (GC) on latency. Moreover, small reads only require a few parallel units, and thus the high-parallel distribution is redundant for the requests. To address this issue, we propose a read-request driven adaptive allocation scheme called RDA to bolster SSD performance by adaptively adjusting the parallel distribution of consecutive pages. The RDA scheme employs the size of historical read requests to gauge the level of parallelism for write requests with varying sizes. Then, RDA allocates the logical pages of writes to distinct parallel units according to the parallelism of the requests. In doing so, RDA effectively mitigates the performance degradation of SSDs caused by redundant parallel distribution, while preserving the parallelism of read requests. We compare RDA with the three state-of-art schemes Amphibian, SOML, and Preemptive GC in terms of GC-blocked read requests, GC counts, and read response time under eight real-world workloads. The experimental results unveil that compared with the existing schemes, RDA revamps the GC-blocked read requests, GC counts, and read response time by averages of 20.6%, 7.8%, and 15.8%, respectively.

Read-disturb problem plays a pivotal factor in the performance of NAND flash memory, because it deteriorates the read-disturb errors of NAND flash. Although ECC, read retry, and read reclaim technologies are designed to correct read-disturb errors, these techniques drastically increase read latency and degrade read performance. Moreover, modern SSDs implement a buffer in the built-in DRAM to store frequently accessed data, which can cache hot read data to alleviate the read-disturb problem. Unfortunately, the buffer primarily serves write requests to curtail write operations in flash memory, and ignores the ever-increasing requirement from users for read latency. To address this issue, we propose a read-disturb-aware dynamic buffer management scheme called Minato that reduces read-disturb errors with rationally read buffer management, aiming to improve the read performance of SSDs. Minato includes two distinctive and vital features. First, Minato dynamically adjusts the size of the read buffer and write buffer through the hit situation of requests, thus increasing the size of the read buffer while maintaining the write hit of the write buffer. Second, to further reduce read-disturb errors, Minato implements a read buffer filter to preferentially cache hot read data disturbing more valid pages into the read buffer. We compare Minato with two state-of-art schemes -BPLRU and GCaR in terms of write hit ratio, read-disturb counts, and read/write response time. The experimental results derived from nine real-world workload traces show that Minato efficiently alleviates the read-disturb problem of flash memory without affecting the write hit ratio, and significantly improves read/write performance. In particular, compared with the existing schemes, Minato slashes the read/write response time by an average of 34.6%.

Multibit 3-D NAND flash-based solid-state disks (SSDs), offering high storage density, contain multiple types of pages to accommodate multiple bits per physical cell. Full sequence program or FSP can program multiple pages in a word line at a time, thereby improving write throughput. Unfortunately, large-grained FSP operations coarsely aggregate consecutive logical pages on the same word line, which adversely affects the parallelism and latency of read requests. Moreover, FSP smooths the program latencies for different types of pages, whereas the pages still exhibit various read latencies. Multiple read latencies and lower read parallelism noticeably deteriorate the completion efficiency of read requests: SSD performance is degraded. To address this issue, we propose an FSP data allocation scheme called FSPDA that incorporates the physical structure characteristics of multibit 3-D NAND, aiming to bolster the read performance of 3-D NAND Flash-based SSDs. FSPDA embraces two distinctive and vital features. First, according to the distance between logical pages, FSPDA allocates logical pages to specified parallel units and stipulates that consecutive logical pages must be assigned to different planes, thus improving read parallelism and data locality. Second, to further reduce read latency, FSPDA employs cache hits to determine hot and cold data to be placed to low-latency and high-latency pages, respectively. We compare FSPDA with two state-of-the-art schemes—OSPADA and single-operation-multiple-location—in terms of multiplane read (MPR) counts, read response time, and GC counts under eight real-world workloads. The experimental results show that compared with the existing schemes, FSPDA slashes the number of MPR counts, read response time, and the number of GC counts by an average of 34.4%, 28.5%, and 13.6%, respectively.

Garbage collection or GC running in the controller of 3-D NAND flash-based solid-state disks—SSDs—plays a critical role in the performance of storage systems. SSD manufacturers have developed various GC solutions based on internal data movement or IDM to mitigate the impacts of GC on request latency. Due to the circuit characteristics of flash memory, the existing IDM-based GC strategies are restricted by page parity during data movement: odd pages must be migrated to odd pages, and even pages to even pages. When migrating two consecutive pages with the same parity, the free page between the two migrated pages will be wasted after the migration is complete. This ever-increasing page waste problem inevitably deteriorates the storage space utilization of flash memory, thereby degrading the overall performance of 3-D NAND flash-based SSDs. To address this issue, we propose a parity-check GC scheme called PcGC to revamp SSD performance by alleviating page waste during GC. We build a parity-check unit in PcGC to facilitate checking the parity of migrated valid pages and destination pages. According to the parity results offered by the parity-check unit, PcGC dynamically adjusts the migration order of valid pages during the course of GC. In doing so, PcGC fundamentally averts page waste caused by the page parity restriction, thereby enhancing 3-D NAND flash performance. We quantitatively evaluate the performance of PcGC in terms of wasted pages, storage utilization, GC counts, write amplification, and average response time. We compare PcGC against the two state-of-the-art schemes—Amphibian and Tiny-tail flash (TTflash). The experimental results derived from the nine real-world workload traces unfold that compared with Amphibian and TTflash: 1) PcGC curtails the number of wasted pages by up to 91.4% with an average of 53.75%; 2) cuts back the number of GC counts by up to 52.2% with an average of 11.9%; and 3) slashes average write response time by up to 77.8% with an average of 13.0%.

A large number of read-disturb-induced rewrites are performed in the background [also known as Read Reclaim (RR)] to alleviate the read-disturb issue in NAND flash memory-based SSDs. RR can significantly degrade the performance and shorten the service life of SSD in read-intensive workloads. To address this issue, we propose a novel read-disturb management approach called Cocktail that mixes a small proportion of hot-read pages with a large proportion of cold-read pages, thereby avoiding clustering hot-read pages into a few blocks. Motivated by the insight that RR operations are frequently triggered by hot read-pages, Cocktail first prefills a portion of each block with cold data extracted from user requests. Then, Cocktail fills the prefilled blocks with write-back data caused by RR to create read-balanced blocks. We integrate two thresholds, write pool capacity and the ratio of RR-write data to User-write data, into Cocktail to govern the ratio of write-back data caused by RR to data of user requests in a block. Cocktail dynamically adjusts the two thresholds according to the characteristics of RR. Cocktail is conducive to decentralizing hot write-back data caused by RR across a broad range of blocks, thereby reducing the occurrence of second-time RR and the number of overall block reads. We compare Cocktail with three existing schemes baseline, redFTL, and IPR in terms of SSD service life, SSD response time, write amplification, and the number of garbage collections (GCs) under ten real-world workload conditions. Experimental results show that compared with the existing schemes, Cocktail reduces the number of RRs, the average response time, the 99-percentile tail latency, and the number of GCs by an average of 40.77%, 10.82%, 5.40%, and 12.29%, respectively. Cocktail also alleviates the write amplification of the three alternative schemes by an average of 49.57%.

Garbage collection (GC) plays a pivotal role in the performance of 3D NAND flash memory, where Copyback has been widely used to accelerate valid page migration during GC. Unfortunately, copyback is constrained by the parity symmetry issue: data read from an odd/even page must be written to an odd/even page. After migrating two odd/even consecutive pages, a free page between the two migrated pages will be wasted. Such wasted pages noticeably lower free space on flash memory and cause extra GCs, thereby degrading solid-state-disk (SSD) performance. To address this problem, we propose a page-state-aware cache scheme called PSA-Cache , which prevents page waste to boost the performance of NAND Flash-based SSDs. To facilitate making write-back scheduling decisions, PSA-Cache regulates write-back priorities for cached pages according to the state of pages in victim blocks. With high write-back-priority pages written back to flash chips, PSA-Cache effectively fends off page waste by breaking odd/even consecutive pages in subsequent garbage collections. We quantitatively evaluate the performance of PSA-Cache in terms of the number of wasted pages, the number of GCs, and response time. We compare PSA-Cache with two state-of-the-art schemes, GCaR and TTflash, in addition to a baseline scheme LRU. The experimental results unveil that PSA-Cache outperforms the existing schemes. In particular, PSA-Cache curtails the number of wasted pages of GCaR and TTflash by 25.7% and 62.1%, respectively. PSA-Cache immensely cuts back the number of GC counts by up to 78.7% with an average of 49.6%. Furthermore, PSA-Cache slashes the average write response time by up to 85.4% with an average of 30.05%.