As semiconductor manufacturing advances toward smaller technology nodes, triple-patterning lithography (TPL) has become indispensable. Existing TPL-aware routers address manufacturability constraints too late, leading to numerous stitches, conflicts, and mask density imbalances. To overcome this, we propose a "shift-TPL-left" strategy that, for the first time, integrates TPL awareness into the track assignment (TA) stage and tightly coordinates it with detailed routing (DR). This approach guides the TPL-aware detailed routing from a more macroscopic level, resulting in faster convergence and fewer DRC violations. Experimental results demonstrate that our method achieves DRC clean in 80% of cases on the ISPD’18 dataset, outperforms the state-of-the-art TPL-aware routing method by 7 × in mask balance score, and achieves a 6 × speedup in runtime.

This paper proposes a novel neural network architecture combining convolutional and transposed convolutional neural networks to accurately and efficiently modelS-parameter of interconnects for 3D integration. The network incorporates physical consistency constraints, specifically causality and passivity, into its design to ensure the physical effectiveness of the output. The transposed convolutional network serves as a sub-network to map the relationship between the geometrical parameters andS-parameter for sub-structures. Then, theS-parameters of individual sub-structures are cascaded for dealing with a complex structure composed of sub-structures. A coupling neural network, with causality and passivity constraints, is developed to map the coarse cascadedS-parameters to the fine accurateS-parameters. With the help of this high-dimensional space mapping, a small amount of electromagnetic simulation data of complex interconnect structures is sufficient to learn the relationship between cascaded and realS-parameters. To ensure the completeness of the training set distribution when training CONN on small datasets, a sensitivity analysis-based training set screening method is proposed to enhance the training performance of CONN. The proposed algorithm is demonstrated in two different assemble structure applications. The results highlight the effectiveness, flexibility and versatility of the proposed architecture in modeling complex structures with small costly simulation data while maintaining accuracy and physical consistency.

Triple patterning lithography (TPL) has been recognized as one of the most promising solutions to print critical features in advanced technology nodes. A critical challenge within TPL is the effective assignment of the layout to masks. Recently, various layout decomposition methods and TPL-aware routing methods have been proposed to consider TPL. However, these methods typically result in numerous conflicts and stitches, and are mainly designed for 2-pin nets. This paper proposes a multipin net routing method in triple patterning lithography, called Mr.TPL. Experimental results demonstrate that Mr.TPL reduces color conflicts by 81.17%, decreases stitches by 76.89%, and achieves up to $5.4 \times$ speed improvement compared to the state-of-the-art TPL-aware routing method.

In this article, we propose an efficient statistical parameter extraction method to accurately model the random device mismatch of MOSFETs. The key idea is to approximate the performance variations as mathematical functions of device mismatch. Based on these approximated functions and the electrical test data, we solve the unknown statistical parameters by nonlinear optimization. Our numerical experiments demonstrate that the proposed method can remarkably improve the modeling accuracy with affordable computational cost, compared against the state-of-the-art techniques.