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Fulun Ma

dblp:345/6019 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 61% Hardware accelerators and domain-specific architectures · 30% Reconfigurable computing and FPGAs · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › design automation tools
accelerator design automation
0.712023
REMAP: A Spatiotemporal CNN Accelerator Optimization Methodology and Toolkit Thereof · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Hardware accelerators and domain-specific architectures › machine learning accelerator
CNN accelerator
0.712023
REMAP: A Spatiotemporal CNN Accelerator Optimization Methodology and Toolkit Thereof · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Electronic design automation
design space exploration
0.712023
REMAP: A Spatiotemporal CNN Accelerator Optimization Methodology and Toolkit Thereof · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Reconfigurable computing and FPGAs › FPGA accelerator
FPGA accelerator implementation
0.212023
REMAP: A Spatiotemporal CNN Accelerator Optimization Methodology and Toolkit Thereof · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023

Methods — techniques the papers use, named apart from their topics

monte carlo tree search · 0.7design space exploration · 0.7
YearPublicationVenuePosition
2023 REMAP: A Spatiotemporal CNN Accelerator Optimization Methodology and Toolkit Thereof
abstract
Designing convolutional neural network (CNN) accelerators is getting more difficult owing to the fast-increasing types of CNN models. Some approaches use constant dataflow and microarchitecture that have lower design complexity. However, these accelerators are difficult to adapt with the highly-diverse CNN models and often suffer from low process element utilization. Some other accelerators resort to reconfigurable devices, such as field-programmable gate array (FPGA) and coarse-grained reconfigurable array to support flexible dataflows in order to fit diverse CNN layers. However, layer-by-layer processing may require more energy for frequent reconfiguration and off-chip DDR access. In this work, we introduce a reconfigurable pipeline accelerator (RPA) that can reduce the latency and DDR access by pipelining the compuptation of CNN layers. Although there have been several researches that try to speedup the design process by automatically exploring subset of the accelerator design space, identifying an available automated design tool that can effectively find the complete and optimal design scheme remains a problem, especially for the novel RPA architecture type. Unfortunately, comprehensive exploration of the whole design space faces an excessive large searching space. To tackle this problem, we propose REMAP, a toolkit for designing CNN accelerators based on the Monte Carlo tree search (MCTS) method. To efficiently search the huge design space, we propose several methods to improve searching efficiency. Evaluations show that REMAP significantly outperforms some state-of-the-art approaches; compared with GAMMA, it achieves an average speed increase of$14.75\times $, and an energy reduction of 45.45%; it also achieves a speed increase of$32.6\times $against ConfuciuX on MobileNetV2 and ResNet50. We also show an FPGA accelerator implementation which is based on REMAP’s search result, and it achieves high performance in real-time CNN tasks. This indicates that REMAP can provide high-quality design exploration with valuable insights and useful architecture design guidances.
Boran Zhao, Tian Xia 0008, Haiming Zhai, Fulun Ma, Hanzhi Chang, Wenzhe Zhao 0001, Pengju Ren
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4