This paper presents a novel accelerator architecture for real-time image filtering applications that require high throughput and low latency. The proposed architecture consists of two systolic arrays: a Row Convolution (RConv) Array and a Column Convolution (CConv) Array. The RConv Array processes one row of the input image and computes one row of an intermediate image per clock cycle which is then input to CConv Array. The CConv Array computes one row of the output image per clock cycle. A novel aspect of the architecture is that the line delays within the convolution architecture are used efficiently due to the parallelism. This leads to a significant reduction in the memory requirement and latency of the architecture. While the row convolution in the RConv Array is implemented using a direct-form FIR filter, the column convolution in the CConv Array is implemented using the transpose-form FIR filter. Thus, the processing elements in the CConv array are implicitly pipelined and do not require additional pipelining delays. The parallelized row-by-row processing significantly reduces the memory overhead per output pixel. The proposed architecture is then generalized where multiple rows of the image can be processed in a clock cycle, leading to further proportional reduction in latency and memory requirements. The proposed architecture is fully feed-forward and can be pipelined further as needed. We show that using a Xilinx Virtex-7 2000T FPGA clocked at 100 MHz, the architecture achieves$16.0\times$,$86.3\times$, and$943\times$improvements in the LUT-time$^2$, FF-time$^2$, and DSP-time$^2$products over a baseline serial architecture for the non-separable case with Image size$128\times 128$and filter size$11\times 11$. The proposed architecture can operate at a throughput of 12.8 Gpixels/s whereas the baseline can only operate at 100 Mpixels/s.

Graph neural networks (GNNs) have emerged as a powerful tool to process graph-based data in fields like communication networks, molecular interactions, chemistry, social networks, and neuroscience. GNNs are characterized by the ultrasparse nature of their adjacency matrix that necessitates the development of dedicated hardware beyond general-purpose sparse matrix multipliers. While there has been extensive research on designing dedicated hardware accelerators for GNNs, few have extensively explored the impact of the sparse storage format on the efficiency of the GNN accelerators. This article proposes SCV-GNN with the novel sparse compressed vectors (SCVs) format optimized for the aggregation operation. We use$Z$-Morton ordering to derive a data-locality-based computation ordering and partitioning scheme. This article also presents how the proposed SCV-GNN is scalable on a vector processing system. Experimental results over various datasets show that the proposed method achieves a geometric mean speedup of$7.96\times $and$7.04\times $over compressed sparse column (CSC) and compressed sparse row (CSR) aggregation operations, respectively. The proposed method also reduces the memory traffic by a factor of$3.29\times $and$4.37\times $over CSC and CSR, respectively. Thus, the proposed novel aggregation format reduces the latency and memory access for GNN inference.