In recent years, the widely collected spatial-textual data has given rise to numerous applications centered on spatial keyword queries. However, securely providing spatial keyword query services in an outsourcing environment has been challenging. Existing schemes struggle to enable top- k spatial keyword queries on encrypted data while hiding search, access, and volume patterns, which raises concerns about availability and security. To address the above issue, this paper proposes OBIR-tree, a novel index structure for oblivious (provably hides search, access, and volume patterns) top- k spatial keyword queries on encrypted data. As a tight spatial-textual index tailored from the IR-tree and PathORAM, OBIR-tree can support sublinear search without revealing any useful information. Furthermore, we present extension designs to optimize the query latency of the OBIR-tree: (1) combine the OBIR-tree with hardware secure enclaves ( e.g., Intel SGX) to minimize client-server interactions; (2) build a Real/Dummy block Tree (RDT) to reduce the computational cost of oblivious operations within enclaves. Extensive experimental evaluations on real-world datasets demonstrate that the search efficiency of OBIR-tree outperforms state-of-the-art baselines by 25x ~ 723× and is practical for real-world applications.

In this paper, a high-noise-immunity capacitive-coupled level shifter with digital noise blanker (DNB) is presented for GaN drivers. During and after$\text{d}V$/dt transitions, the DNB blanks the common mode noise induced by$\text{d}V$/dt and converts the differential mode noise due to mismatch effect to common mode noise. This enables high$\text{d}V$/dt immunity of 200V/ns and high mismatch tolerance not less than 15%. Moreover, a dynamic discharge control (DDC) circuit prevents coupling capacitor from charging the floating power rail within a wide negative$\text{d}V$/dt transition range and achieves fast reset for high frequency operation. High speed, low power consumption and down to −5V negative floating power rail tolerance are also achieved. The proposed level shifter is fabricated in a 0.5-$\mu \text{m}$BCD process and occupies an active chip area of 0.051mm2. Experimental results confirm that the proposed level shifter works at 50V 50MHz, achieving power consumption of 27.3pJ/transition and 1.26ns average delay with a small figure of merit (5.5(pJ$\cdot $ns)/($\mu \text{m}^{3}\cdot \text{V}$)). The effect of the DDC is confirmed within negative$\text{d}V$/dt transition range of −5V/ns$\sim -50\text{V}$/ns.