Over the past decade and beyond, standard cell layout generation has been a cornerstone of digital integrated circuit design, evolving from manual design practices to advanced AI-assisted methodologies. This survey systematically reviews the evolution of standard cell layout generation across two major axes: methodological advances and transistor and cell architecture changes. First, we trace the methodological progression from manual design practices and early design-rule-based approaches to heuristic algorithms, exact optimization methods, and the most recent AI-driven paradigms. Then, we examine the evolution of transistor and cell structures: The transistor from planar CMOS to the emerging vertical devices (CFETs and Flip-FETs); and the cell architecture from the multi-row structures to the integration of buried power rails (BPR) and backside metal layers. Finally, we highlight future research directions including transistor–cell–chip co-design methodologies, optimization techniques that leverage unique electrical characteristics of emerging CMOS devices. This comprehensive survey aims to provide insights into current state-of-the-art techniques while highlighting promising avenues for future innovation in standard cell layout generation for next-generation technologies.

As semiconductor technology continues to scale, standard cell layout generation becomes increasingly challenging, yet remains critical for Design Technology Co-Optimization (DTCO). This paper presents a satisfiability modulo theories (SMT)-based methodology that tightly integrates transistor folding and placement to optimize standard cell layouts. Our approach offers two key contributions: (1) a unified SMT-based framework for simultaneous transistor folding and placement, which explores folding configurations beyond mandatory constraints to achieve globally optimal placement with improved area and routability; and (2) a mono-dummy insertion strategy based on the longest common subsequence (LCS) algorithm, which aligns PMOS and NMOS transistor chains to enhance diffusion sharing and further reduce layout area. Experimental results using the ASAP7 7 nm PDK show that our SMT-based transistor placement framework produces fully routable layouts with $4.12 \%$ smaller average cell area compared to manually crafted counterparts. Moreover, when combined with heuristic in-cell routing, our method successfully generates layouts for 172 standard cells, including complex cells such as high fan-in gates and flip-flops with asynchronous reset, with transistor placement completing in 836.7 seconds. This work demonstrates that our simultaneous optimization of transistor folding and placement enables both higher layout quality and practical automation for advanced standard cell design.

In standard-cell-based VLSI design, fixed margins at cell boundaries are necessary to prevent short violations between adjacent transistors carrying different signals. However, these margins are redundant for most abutted cell pairs and incur non-negligible area overhead when accumulated across the chip. In this paper, we present a novel VLSI design optimization framework that eliminates redundant margins by strategically merging adjacent cells into margin-free cells (MF-cells), which preserve the same functionality with reduced area due to the removal of inter-cell margins. Precisely, we identify optimal cell pairs for merging from an initial standard-cell-based placement using a maximum weighted matching (MWM) algorithm. Each identified pair is replaced with an MF-cell and placed at an optimal position using a placement algorithm that minimizes wirelength and routing congestion. Compared to the conventional standard-cell-based design, we achieve on average 3.9% reduction in total cell area and 4.7% reduction in full chip area, leading to 2.7% reduction in total wire length and 2.1% improvement in timing performance while maintaining comparable power consumption. Our framework is a practical approach to achieve meaningful area and timing improvements, which is fully compatible with commercial standard-cell-based VLSI design flow.

As semiconductor technology scales beyond 5 nm, complementary FET (CFET) that stacks P-FET and N-FET enables extreme cell area scaling. However, reduced standard cell height with CFET presents routability challenges due to limited back-end-of-line (BEOL) routing resources. In this paper, we address two key routability problems, i.e., pin accessibility and routing congestion, by employing various pin-extended cells on demand. Moreover, we introduce an end-to-end VLSI design framework that further alleviates routing congestion using partial placement blockages. Experimental results demonstrate that our framework eliminates most design rule violations (DRVs) related to routability while maintaining the area advantages of CFET technology.

This article presents a continuous-time (CT) linear-exponential incremental ADC (IADC) that achieves 15-bit resolution at 250kHz bandwidth with 40 cycles for one conversion. It is based on an energy-efficient CT linear-exponential IADC, which alleviates the requirements of the power-hungry input buffer and loop filter. The proposed IADC employs a coarse 9-bit first-order IADC followed by a fine 8-bit cyclic ADC. The first-order IADC performs the coarse conversion by linearly accumulating input signals, resulting in a small thermal noise penalty. The residual quantization noise is exponentially reduced by the cyclic ADC, significantly shortening the conversion cycle. The cyclic ADC achieves the required accuracy by reconfiguring the loop filter of the coarse IADC and effectively compensating for the excessive loop delay. The prototype CT IADC is fabricated in a 65-nm CMOS process. With a 20MHz clock, it achieves 88.6-dB SNDR, 89.3-dB SNR, 90.1-dB DR, and 103.1-dB SFDR at a conversion rate of 500 kS/s. It consumes only 2.4 mW from a 1.2 V supply. It achieves the Schreier FoM (SNDR) of 168.8dB.