Demo Data from EDBT 2026 / reviewers in the wild / expert
Neidong Fu
dblp:348/0358
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2023
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 67% Storage systems · 33% | |
| Theoretical computer science
1 paper |
Coding theory · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Storage systems › data representation › data encoding › error correction coding
LDPC codes |
0.7 | 1 | 2023 | eLDPC: An Efficient LDPC Coding Scheme for Phase-Change Memory · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Memory systems
non-volatile memory |
0.7 | 1 | 2023 | eLDPC: An Efficient LDPC Coding Scheme for Phase-Change Memory · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Memory systems › non-volatile memory
phase change memory |
0.7 | 1 | 2023 | eLDPC: An Efficient LDPC Coding Scheme for Phase-Change Memory · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Coding theory
error-correcting codes |
0.2 | 1 | 2023 | eLDPC: An Efficient LDPC Coding Scheme for Phase-Change Memory · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Coding theory › error-correcting codes
LDPC codes |
0.2 | 1 | 2023 | eLDPC: An Efficient LDPC Coding Scheme for Phase-Change Memory · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | eLDPC: An Efficient LDPC Coding Scheme for Phase-Change MemoryabstractLow read latency, long lifetime, and high storage density have all been demonstrated in phase-change memory (PCM), making it an attractive contender for main memory. However, due to resistance drift per cell caused by long-term storage, data reliability becomes a major challenge. Low-density parity-check (LDPC) codes with improved error correction capability can be used in PCM to reduce bit error rates and thus improve data reliability. More interestingly, when the raw bit error rates (RBERs) of various pages in PCM is compared at the same storage time, a considerable gap appears, resulting in high sensing and decoding latency. We propose eLDPC, an efficient LDPC coding scheme for reducing sensing and decoding latency, in this article. We start with a preliminary experiment, which reveals that there is a significant variation in resistance drifts between adjacent distributions, resulting in a large RBER gap for different pages. Then, using a submatrix of the parity-check matrix to shorten the codeword length, eLDPC is inspired to encode pages with lower RBER. The original bit sequence is separated into even bit sequence (EBS) and odd bit sequence (OBS) for pages with higher RBER. eLDPC is used to encode EBS and OBS independently. By utilizing optimized soft information, EBS and OBS are eLDPC decoded. eLDPC can significantly improve the error correction capability of LDPC hard decoding, effectively eliminating soft decoding processes, and lowering decoding latency. The results of simulations show that eLDPC can greatly decrease decoding iterations and time. Meng Zhang 0014, Fei Wu 0005, Neidong Fu, Changsheng Xie 0001 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 4 |