Adaptive modulation and coding (AMC) systems require the transmission of control signals, thereby reducing overall system transmission efficiency. The channel coding blind recognition technique is key to solving this problem. This paper proposes a reduced-complexity method for blind recognition of low-density parity-check (LDPC) coding parameters within a given candidate set, thereby enhancing the work efficiency of AMC systems. This paper applies a method based on code rate for classification evaluation, circumventing superfluous calculations for several candidate parity-check matrices. Furthermore, computational complexity is reduced by applying the offset min-sum algorithm (OMSA) to the parity-check stage. Subsequently, the Z-score is used to measure the difference between the actual data and the theoretical distribution. Compared with the best existing recognition methods, the proposed algorithm offers clear advantages in computational complexity and is virtually identical in recognition performance.

In non-cooperative communication systems, recognition and decoding are two key technologies that determine whether the receiving terminal can correctly decipher the information. To better utilize the prior information by recognition and improve the decoding performance, a novel frequency domainlow complexity chase (F-LCC) Reed–Solomon (RS) decoding scheme is proposed. Firstly, the relationship between recognition and decoding is analyzed, and the erroneous codewords to be decoded can be selected by analyzing the spectrogram obtained from recognition; Then, the$\eta$-dynamically adjustable multiplicity assignment ($\eta$-DAMA) algorithm is proposed by analyzing the channel soft information, where$\eta$is the number of the most unreliable code positions. Wherein, the number of test vectors$2^{\eta }$is modeled as a function of code length and bit error rate (BER), which solves the problem of traditional decoding algorithms relying on empirical values to determine$\eta$. Simulations verify the frame error rate (FER) of the proposed F-LCC for decoding RS(255,239) with different signal-to-noise ratios (SNRs). The results show that the proposed F-LCC decoding scheme can achieve a gain of 0.3dB and 0.15dB compared with the decoding performance of the existing time domain-LCC (T-LCC) decoding scheme when$\eta$= 3 and$\eta$= 5, respectively.

This letter presents an RS-SPC concatenated code blindrecognition algorithm based on the single-error correction. The algorithm corrects the least reliable bit of the single parity check (SPC) codewords based on the parity check characteristics, thereby increasing correct Reed-Solomon (RS) codewords and laying the foundation for improving the recognition probability. In addition, this algorithm combines threshold judgement with the matrix recording method, thereby eliminating unnecessary iterative operations under the condition that accurate recognition is possible. At the same time, it employs probability theory as a theoretical basis to quantify the degree of dispersion of the data through sample variance. The experimental results demonstrate that the recognition probability of this algorithm is superior to that of all other algorithms. When the codeword error rate (CER) is 0.5, RS(15,9)-SPC(4,3) still has a recognition probability of 20%. For RS(255,239)-SPC(8,7), the gain of the proposed algorithm exceeds 1.3dB compared to the upper bound of the recognition probability.

This paper proposes a full-blind recognition method that aims to recognize coding parameters from a noisy bitstream of limited BCH and RS codes intercepted in a non-cooperative communication system under harsh channel environments. This paper optimizes the codeword reliability calculation by fully utilizing channel soft information, based on which the single-bit error codewords can be effectively selected from the codeword stream with a high probability. Subsequently, the channel soft information-based single-error correction (CSI-SEC) algorithm is proposed for correcting single-bit error codewords. The blind recognition algorithm, based on the Galois domain Fourier transform (GFFT) with a dual decision-making mechanism, is applied to these corrected codewords and reliable codewords to extract the encoding parameters. Finally, the method’s superiority is demonstrated through comprehensive simulation experiments. Compared to other blind recognition methods based on error correction, the proposed method exhibits enhanced recognition performance, with a cumulative computational complexity of only 39.8% of that of the other methods. Compared to other algorithms for blind recognition of limited intercepted bitstream, the proposed method achieves at least a 3 dB improvement in recognition performance.

In this article, an area-efficient VLSI architecture scheme for high-throughput computation of the 2-D discrete wavelet transform (DWT) is proposed, effectively applied in the context of aircraft cargo hold scenes. The proposed architecture aims to reduce computation and storage resources while maintaining the DWT-IDWT reconstructed image quality for the 9/7 discrete wavelet. The hardware implementation formulae based on the flipping architecture have been modified to reduce RAM storage bit width. By transforming the coefficients of the formula into hardware-friendly values, the required multiplication operations are split into two stages of addition. On this basis, a pipelined architecture is constructed to set the critical path delay (CPD) of the architecture to be close to the delay of a single adder,$T_{a}$, thereby achieving a high throughput. Compared to existing architectures in the research field, the proposed single-level 2-D DWT architecture achieves resource savings on the field-programmable gate array (FPGA) platform while ensuring good image reconstruction quality. The advantages of the multilevel 2-D DWT are even more pronounced. In the simulation results on the application-specific integrated circuit (ASIC) platform, the proposed architecture reduces computation time by at least 35.54% while achieving a higher level of decomposition, decreases the area-delay product (ADP) by at least 25.41%, and saves a significant amount of energy per image (EPI). Furthermore, the proposed folded architecture achieves close to 100% hardware utilization efficiency (HUE) in multilevel 2-D DWT computations.

Multiple quantization (MQ) encoder is a basic entropy encoder widely used in multimedia encoding systems, especially in JPEG2000 and JBIG2, which play a key role and make outstanding contributions to digital imaging. However, due to its strict serial working characteristics, the MQ encoder has become a key bottleneck restricting the optimization of JPEG2000 encoding performance. Many single ejection encoder architectures use pipeline staging to improve the throughput, but they have all reached their limits. A high-performance MQ encoder based on a novel lookup table is proposed to overcome this bottleneck, which improves the throughput while utilizing reasonable hardware resources and with low-power consumption. Experimental results show that the proposed encoder architecture can encode two symbols per cycle with a throughput of 1204.82 MSymbol/s, and it has a power consumption of only 11.05 mW. Compared with the conventional multi-context coder, the hardware utilization is reduced by 26%, and the hardware utilization efficiency is improved by 16%. Compared with the conventional single-context coder, the throughput is improved by 14.3%, and the power consumption is reduced by 40.1%.