The continued scaling of CMOS technology amplifies the challenges of delivering power efficiently to many-core processors. Dynamic voltage and frequency scaling (DVFS) offers substantial energy savings, but its effectiveness depends on the voltage settling time, efficiency, and integration cost of the underlying regulators. This paper presents a system-level evaluation of monolithic 3D (M3D) per-core DC–DC converters for fine-grained DVFS in many-core CPUs. Using workload traces extracted from gem5 and an energy modeling framework that accounts for regulator efficiency, power delivery network (PDN) parasitics, transition overheads, and area, we compare five representative configurations across 8-, 16-, and 32-core systems. Results show that off-chip converters with global DVFS achieve only ~24% average energy reduction, on-chip per-core DVFS improves this metric to ~41%, and M3D per-core DVFS delivers the highest savings at ~43% while also minimizing die area by up to 20% relative to on-chip converters and 38% relative to off-chip solutions. These findings underscore the importance of localized regulation and vertical integration for designing scalable, energy-efficient processors in future generations.

The Last Level Cache (LLC) is the processor’s critical bridge between on-chip and off-chip memory levels - optimized for high density, high bandwidth, and low operation energy. To date, high-density (HD) SRAM has been the conventional device of choice; however, with the slowing of transistor scaling, as reflected in the industry’s almost identical HD SRAM cell size from 5 nm to 3 nm, alternative solutions such as 3D stacking with advanced packaging (i.e., hybrid bonding) are pursued (as demonstrated in AMD’s V-cache). Escalating data demands necessitate ultra-large on-chip caches to decrease costly off-chip memory movement, pushing the exploration of device technology towards monolithic 3D (M3D) integration, where transistors can be stacked in the back-end-of-line (BEOL) at the interconnect level. M3D integration requires fabrication techniques compatible with a low thermal budget (seconds) when used in a gain-cell configuration. This paper examines device, circuit, and system-level tradeoffs made when optimizing BEOL-compatible AOS-based 2-transistor gain cells (2T-GC) for LLC. A cache early-exploration tool, NS-Cache, is developed to model caches in advanced 7 & 3 nm nodes and is integrated with the Gem5 simulator to systematically benchmark the impact of the newfound density/performance when compared to HD-SRAM, MRAM, and 1T1C eDRAM alternatives for LLC.

We present the first security and disturbance study of monolithic 3D (M3D) embedded DRAM (eDRAM) with 2T gain cell using oxide-channel transistors. We explore the Rowhammer/Rowpress vulnerabilities on amorphous indium tungsten oxide (IWO) transistors for eDRAM with standalone 2D integration and memory-on-memory M3D integration. In addition, We examine M3D-specific electrical disturbances from memory-on-logic M3D integration. We evaluate IWO eDRAM's susceptibility to these vulnerabilities/disturbances and discuss the potential impact on M3D integration. We examine physical design and architecture strategies for M3D integration of IWO eDRAM. We provide systematic recommendations to inform security strategies for M3D integration and security of IWO eDRAM. Our results show that limiting the minimum vertical interlayer distance to 300 nm reduces vertical disturbances in memory-on-memory M3D integration. In addition, for memory-on-logic M3D integration, we observed that IWO eDRAM's read bitline is sensitive to crosstalk from high-speed switching logic circuits. In conjunction, we show that IWO eDRAM standalone 2D integration is 30× more resilient to Rowhammer than current state-of-the-art memory because the IWO transistor's$I_{ON}/I_{OFF}$ratio is roughly three orders of magnitude greater than standard memory access transistors.

The increasing demand for energy-efficient computing has created the need for advanced power management solutions. Backside power delivery network (BSPDN) has been introduced in the industry for 2-nm node with passive wires. In this work, we propose adding active components (power transistors) to the backside of silicon in a back-end-of-line (BEOL)-compatible fabrication process. The goal is to enable 12–0.7-V voltage downconversion at the backside of silicon (near the point of load, i.e., the frontside logic compute die) to minimize the IR drop and improve overall system-level conversion efficiency. This work leverages a hybrid monolithic 3-D (M3D)dc-dc converter architecture combining switched-capacitor (SC) and synchronous buck converter topologies with BEOL-compatible active and passive devices. The design employs amorphous tungsten-doped indium oxide (IWO) transistors, which offer high breakdown voltage and tunable threshold voltages, supporting both enhancement and depletion modes for efficient switching. With the experimentally calibrated compact models, the simulated hybrid converter design achieves 12–0.7-V conversion with a peak efficiency of 95.6% at a power density of 330 mW/mm2, demonstrating the feasibility of M3D SC dc-dc converters for next-generation power management in high-performance edge devices.

The rising computational demands of artificial intelligence (AI) models are driving increased data transfers from off-chip DRAM, resulting in increased energy consumption and latency. With the conventional Von-Neumann architecture nearing its limits, Near-Memory-Compute (NMC) and In-Memory-Compute (IMC) have emerged as potential alternatives, aiming to minimize memory access by computing directly within memory. The choice between IMC and NMC is contingent on the specific needs of an application, especially when balancing throughput and accuracy. While conventional SRAM is not optimized for extensive parallel computation due to its large footprint, 2T gain-cell (GC) embedded DRAM (eDRAM) presents a favorable alternative. However, its integration with IMC and NMC poses challenges in terms of chip size and data retention. We propose that monolithic three-dimensional (M3D) 3T transposable GC eDRAM with tungsten-doped indium oxide channel (IWO) back-end-of-line (BEOL) transistors to efficiently mitigate these challenges. The benchmark results show that 3T IWO GC eDRAM has 60 % area reduction compared to 10T Si SRAM. Furthermore, the data retention of the proposed design is ~104times longer than that of 3T Si GC eDRAM. The comprehensive study from technology to architecture highlights the potential of the 3T IWO GC eDRAM as a robust candidate for L4 cache and parallel computing.