Xinda Chen

dblp:348/5083 · DBLP profile ↗
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4ranked-venue papers
2as first author
4since 2021 · last 2026
0000-0002-7421-9326ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021Artificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 83% Emerging computing paradigms · 8% Integrated circuit design · 8%
Interdisciplinary, comprehensive, and emerging computing
1 paper
Medical and health informatics · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › routing › timing-driven routing
length-matching routing
1.012026
JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits · IEEE Trans. Computers 2026
Electronic design automation
physical design
1.012026
JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits · IEEE Trans. Computers 2026
Electronic design automation › physical design
placement and routing
1.012026
JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits · IEEE Trans. Computers 2026
Integrated circuit design › superconducting logic
rapid single-flux-quantum circuits
0.312026
JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits · IEEE Trans. Computers 2026
Emerging computing paradigms › beyond-CMOS computing
superconducting computing
0.312026
JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits · IEEE Trans. Computers 2026
Medical and health informatics
multimodal clinical data
0.312025
Multimodal Inference with Incremental Tabular Attributes · IJCAI 2025

Methods — techniques the papers use, named apart from their topics

maximum flow · 1.0left-edge algorithm · 1.0dynamic programming · 1.0encoder · 0.9disentangled representation · 0.9consistency loss · 0.9
YearPublicationVenuePosition
2026 RECALLS: Reinforcement Learning Enhanced Generative Model for Logic Synthesis Optimization
Xinda Chen, Rongliang Fu, Chunyang He, Tsung-Yi Ho, Junying Huang
ISCAS2
2026 JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits
abstract
Superconducting rapid single-flux-quantum (RSFQ) logic is a promising candidate for advancing future computing technologies due to its low-energy consumption and high-frequency capabilities. However, precise timing alignment is crucial for its physical design, posing significant challenges in length-matching placement and routing. This paper introduces JPnR, a physical design framework tailored for RSFQ circuits, featuring a clock-aware length-matching placer and a length-matching multi-terminal router. The placer simultaneously considers both clock distribution and timing constraints, distributing clock pulses heuristically and transforming the placement problem into a single-source shortest-path problem. This allows it to minimize vertical wirelength using dynamic programming and iteratively optimize placement via a barycenter-like reordering method. The router tackles challenges related to splitter placement and length-matching multi-terminal routing using a two-layer planar Manhattan routing model. Initial routing assigns tracks based on the left-edge algorithm to minimize routing width while employing the dogleg algorithm to resolve cycles in the vertical constraint graph. Length-matching is achieved via a splitter tree-based hierarchical approach with maximum-flow-based detour insertion. Finally, a PTL region expansion strategy is employed for unsatisfied connections. Experimental results on RSFQ benchmarks demonstrate the effectiveness and efficiency of JPnR.
Rongliang Fu, Minglei Zhou, Xinda Chen, Junying Huang, Xiaochun Ye, Zhimin Zhang 0004, Tsung-Yi Ho
IEEE Trans. Computers4
2025 Multimodal Inference with Incremental Tabular Attributes
abstract
Multimodal Learning with visual and tabular modalities has become more and more popular nowadays, especially in the healthcare area. Due to the adaptation of new equipment or new factors being introduced, the tabular modality keeps changing. However, the standard process of training multimodal AI models requires tables to have fixed columns in training and inference; thus, it is not suitable for handling dynamically changed tables. Therefore, new methods are needed for efficiently handling such tables in multimodal learning. In this paper, we introduce a new task, multimodal inference with incremental tabular attributes, which aims to enable trained multimodal models to leverage incremental attributes in tabular modality during the inference stage efficiently. We implement a specialized encoder to disentangle the latent representation of incremental tabular attributes inside itself and with the old attributes to reduce information redundancy and further align the incremental attributes with the visual modality with consistency loss to improve information richness. Experimental results across five public datasets show that our method effectively utilizes incremental tabular attributes, achieving state-of-the-art performance in general scenarios. Beyond the inference, we also find that our method achieved better performance in fully supervised settings, evoking a new training style for multimodal learning with tables.
Xinda Chen, Zixian Zhang, Weimin Tan
IJCAI1
2023 JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits
abstract
Superconducting rapid single-flux-quantum (RSFQ) logic has shown great potential for high-energy-efficient computing systems. To ensure correct operations at ultra-high frequencies, it is necessary to incorporate length-matching constraints into the routing problem. Existing routing algorithms, however, can only address 2-pin connections or support the conventional horizontal/vertical routing model, which substantially limits the optimization space for routing solutions. This paper presents JRouter, an RSFQ router that considers the two-layer planar Manhattan routing model while simultaneously coping with splitter (SPL) placement and length-matching multi-terminal routing. JRouter contains a track-assignment-based initial routing that minimizes the initial routing width while avoiding conflicts in the horizontal constraint graph. Moreover, JRouter implements an SPL-tree-based hierarchical routing with an iterative maximum-flow-based formulation to insert the detours for multi-terminal routing. A routing region extension algorithm is also developed to insert the detours for unsatisfied connections. According to the experimental results, JRouter achieves an average routing width reduction of 35.71% and 22.46% on a 16-bit RSFQ Sklansky adder compared to Kito's and Kou's routing algorithms. For randomly generated benchmarks, JRouter reduces the routing width by an average of 38.77%, 38.20%, 21.65%, and 7.01% compared to Kito's, Kou's, and two of Yan's routing algorithms, respectively, while maintaining reasonable runtime.
Xinda Chen, Rongliang Fu, Junying Huang, Huawei Cao, Zhimin Zhang 0004, Xiaochun Ye, Tsung-Yi Ho, Dongrui Fan
ACM Great Lakes Symposium on VLSI1