Continued technology scaling and ever shrinking feature sizes in Integrated Circuit (IC) layouts cause those layouts to look like highly idealized versions of the true structures on a manufactured IC. However, there are a number of instances where we need to be able to link the ideal and manufactured layouts like for quality control and reverse engineering. The imaging of ICs is performed via Scanning Electron Microscopy (SEM). It is a complex and expensive process which is invaluable when debugging technology problems or finding circuit defects. An alternative is SEM or Lithography Simulation, where physics-based models of the imaging process can be used to predict the manufactured layout, which is also is highly complex and resource consuming process. Data-driven simulators also suffer from the limited amount of publicly available IC design data for training. In this paper, we present GDS2SEM, a data-driven and diffusion-based alternative to understanding the relationship between ideal and manufactured layouts, which can help us generate new Layout-SEM image data. We formulate the Layout-to-SEM mapping as a machine learning image-to-image translation task. We show that it is possible to create such an accurate mapping, and demonstrate it on a number of layouts. We also showcase the potential that this method holds for data augmentation by testing its generative capabilities on unseen data.

Processing In-Memory (PIM) is a data-centric computation paradigm that performs computations inside the memory, hence eliminating the memory wall problem in traditional computational paradigms used in Von-Neumann architectures. The associative processor, a type of PIM architecture, allows performing parallel and energy-efficient operations on vectors. This architecture is found useful in vector-based applications such as Hyper-Dimensional (HDC) Reinforcement Learning (RL). HDC is rising as a new powerful and lightweight alternative to costly traditional RL models such as Deep Q-Learning. The HDC implementation of Q-Learning relies on encoding the states in a high-dimensional representation where calculating Q-values and finding the maximum one can be done entirely in parallel. In this article, we propose to implement the main operations of a HDC RL framework on the associative processor. This acceleration achieves up to \(152.3\times\) and \(6.4\times\) energy and time savings compared to an FPGA implementation. Moreover, HDRLPIM shows that an SRAM-based AP implementation promises up to \(968.2\times\) energy-delay product gains compared to the FPGA implementation.

This paper summarizes the talks of a special session on the IPF 2.0 project, a collaborative German-US research project that leverages self-awareness principles for the self-management of distributed systems of autonomous multiprocessor systems-on-chip (MPSoCs).

The Information Processing Factory (IPF) utilizes factory management principles to tackle the complexities of integrated embedded systems, ensuring continuous safe operation and optimization at runtime. This paper presents a hardware implementation of IPF that enables dynamic task migration across system resources, ensuring reliability in the face of internal or external failures. We demonstrate the effectiveness of IPF through the efficient migration of tasks in multiprocessor SoCs using a safety-critical pacemaker application as a case study. Despite the additional software and hardware requirements, implementing IPF in a pacemaker results in comparable reliability to dual modular redundancy (DMR) with faster service resumption and improved resource utilization.