The increasing complexity of modern processor designs has posed significant challenges in achieving comprehensive coverage metrics for functional verification of Register-Transfer Level (RTL) designs. Despite the availability of white-box RTL models, recent advancements in hardware fuzzing have predominantly focused on grey-box methodologies, which lack effective utilization of internal logic and structural information.This paper presents a novel approach that addresses this limitation by extracting control flow graphs (CFGs) from processor designs and analyzing the dependencies within these graphs. The analyzed CFGs serve as heuristic information to guide the generation of processor stimuli. By effectively leveraging internal logic information during the simulation of complex processors, this method provides interpretable heuristics for test generation. Experimental results demonstrate the effectiveness of utilizing control flow information derived from processor designs in enhancing the convergence speed of coverage metrics and guiding test sequences towards hard-to-reach states.

Verification is critical in ensuring the reliable operation of modern, complex computing systems. However, as processor designs become increasingly sophisticated, conventional static verification techniques struggle to generate high-quality test sequences that achieve comprehensive coverage. Dynamic simulation-based approaches, which leverage coverage-driven objectives, can increase confidence in correct processor functionality but often suffer from low verification efficiency due to the generation of redundant test sequences and significant computational overhead. To address these challenges, this paper presents DeepVerifier, a novel coverage-guided test generation framework that leverages data-driven learning of existing test sequences and their associated coverage feedback. DeepVerifier uses a language model to learn the semantic representations of test sequences, ensure adherence to syntax constraints, and estimate the relationship between test sequences and coverage scores. By updating test sequences with higher coverage, DeepVerifier can significantly improve the efficiency and effectiveness of the verification process. Experimental results of verifying an out-of-order RISC-V microprocessor demonstrate that the framework accurately estimates the coverage scores of test sequences and updates high-quality sequences that contribute to higher coverage. This coverage-guided test generation technique holds promise for enhancing the reliability of modern processor designs.

Functional verification is critical in ensuring the correctness of register transfer level (RTL) models. Formal methods, such as model checkers, are powerful tools that help achieve high coverage in functional validation by transforming the coverage problem into property verification tasks. However, these methods typically demand significant memory usage and long verification times. One major issue is that the satisfiability problem for each unsolved property always starts from the reset state of a design, leading to repeated solving of the same subset of clauses across different properties. In this paper, we propose an open-source semi-formal framework based on model checkers that accelerates test stimulus generation through two techniques: assertion ordering and strategic selection of starting states. These techniques enable model checkers to intelligently select starting states that are much closer to the final state, thereby reducing unnecessary computations. Through comprehensive experiments on ITC'99 benchmarks and modern complex processor designs, including OpenCores 1200 and Rocket-Chip, we demonstrate that our proposed techniques can achieve higher coverage with less than half of the test generation time.

The validation of Register-Transfer Level (RTL) models requires achieving sufficient branch coverage. However, automatically activating all branches in RTL models is challenging, considering the complexity of modern designs. While traditional methods, such as model checkers, can achieve high coverage, they typically demand substantial computational resources to solve formal equations. In contrast, constraint-random approaches have better scalability but suffer from inefficiency due to poor heuristics. This paper introduces APE-FV, a Concolic testing framework designed for RTL functional verification to effectively cover rare branches. APE-FV dynamically modifies the path exploration strategy by considering structural information, simulated paths, and states. Additionally, our framework incorporates an incremental exploration technique, which reduces the burden on solvers and enhances efficiency. Experimental results demonstrate that our approach accelerates the verification process and maintains high coverage, outperforming state-of-the-art techniques.

Recent years have seen a surge in Internet of Things (IoT) technologies, with billions of mobile devices (MDs) straining limited computing and networking resources. Mobile edge computing offloads tasks from MDs to edge servers, saving energy and reducing network pressure. Edge servers provide closer services yet have fewer resources than cloud servers. A new heterogeneous edge and cloud computing paradigm combines the benefits of both. Edge servers provide close proximity services to MDs, while the cloud owns enough resources. The existence of mobile IoT devices makes it more practical to consider mobility when allocating resources of edge servers to decrease the energy consumption of the heterogeneous edge and cloud while meeting the latency needs of tasks. This work formulate a constrained energy consumption optimization problem and design a hybrid algorithm named Genetic Simulated-annealing-based particle swarm optimization (PSO) to yield a near-optimal solution. Simulation results prove that compared to genetic algorithm, PSO, simulated-annealing-based PSO, and Trex, GSPSO reduces the total energy consumption by 38.64%, 54.63%, 45.94%, and 36.21%, respectively.

Branch coverage is important in the functional val-idation of Register-Transfer-Level (RTL) models. While random tests can cover the majority of easy-to-reach branches, there are still many hard-to-activate branches in today's industrial designs. These remaining corner branches are typically the source of bugs and hardware trojans. Directed test generation approaches using formal methods effectively activate a specific branch but are limited by the state explosion problem. Semi-formal methods, such as concolic testing, improve the scalability by exploring one path at a time. This paper presents a novel concolic testing framework to exercise the corner branches through state tracing-based search heuristics (STSearch). The proposed approach heuristically gen-erates and evaluates input sequences based on a novel heuristic indicator that evaluates the distance between the current state and the target branch condition. The heuristic indicator is designed to utilize both the static structural property of the design and the state from dynamic simulation. Compared to the existing concolic testing approaches, where a full new path is generated in each round by solving path constraints, the cycle-based heuristic search in the proposed approach is more effective and efficient. Experimental results show that our approach significantly outperforms the state-of-the-art approaches in both running time and memory usage.