Artificial Intelligence hardware accelerators are pervading the chip market. Most of the time, they are third-party IPs integrated by silicon manufacturers. As a consequence, their design may be obfuscated, which can introduce issues from a manufacturing testing perspective. This paper illustrates how to effectively and efficiently select the most appropriate functional stress stimuli for Artificial Intelligence (AI) Hardware (HW) Accelerators embedded in System-on-Chip (SoC). The proposed methodology is netlist independent; and it is based on both current measurements from the real chip and architectural evaluations. These ingredients are heuristically used to rank and sift the optimal functional patterns to apply along the Burn-In (BI) phase. Experimental results on two different Automotive SoCs manufactured by STMicroelectronics, demonstrate the effectiveness and efficiency of the proposed method.

This paper proposes a novel multi-site functional testing methodology for hardware timers, essential components in safety-critical systems. The methodology employs a custom flexible tester modified for JTAG-based multi-site testing, enabling simultaneous evaluation of multiple devices under test (DUTs) alongside a golden chip for reference. By varying voltage and frequency conditions, the DUT’s timer behaviour is compared to the golden chip’s to identify faults such as transition delay and small delay faults. Experimental results demonstrate the effectiveness of the methodology in enhancing reliability and ensuring compliance with stringent safety standards like ISO26262 and DO-178C. This approach provides a scalable and adaptable solution for testing complex SoC designs in diverse safety-critical applications.

This paper deals with functional System-Level Test (SLT) for System-on-Chips (SoCs) communication peripherals. The proposed methodology is based on analyzing the potential weaknesses of applied structural tests such as Scan-based. Then, the paper illustrates how to develop a functional SLT programs software suite to address such issues. In case the communication peripheral provides detection/correction features, the methodology proposes the design of a hardware companion module to be added to the Automatic Test Equipment (ATE) to interact with the SoC communication module by purposely corrupting data frames. Experimental results are obtained on an industrial, automotive SoC produced by STMicroelectronics focusing on the Controller Area Network (CAN) communication peripheral and showing the effectiveness of the SLT suite to complement structural tests.

Functional test programs are increasingly used as flexible approaches to verify device functionality, both online (e.g., Software-Based Self Tests encapsulated in Software Test Library) and during the manufacturing test flow (e.g., System-Level Test). However, a traditional integrated development environment seldom analyzes functional test program weaknesses regarding fault-masking and propagation in CPU registers. Therefore, understanding the presence of errors in the programs due to logic faults at the end of the test program is only assessed by a signature computation, e.g., xor operation between all registers. The presence of program weaknesses in terms of data or control flow is not assessed, and it may lead to fault escapes and/or masking. In particular, those are perfect conditions for proliferating Silent data corruption and unrecoverable errors at the system level.This work aims to introduce a guided debugger-based fault injector framework to verify the fault propagation and masking capabilities of functional test programs by eventually catching program errors without relying on time-consuming simulation-based approaches. The fault-free instruction trace is dumped and analyzed to provide information about possible target registers of specific instructions for injecting faults, e.g., in jump instructions, where errors into registers may change the execution flow or not, to verify the presence of silent data corruptions and errors.The experimental results are carried out on an automotive device from the SPC58 family manufactured by STMicroelectronics, and faults are injected through a script running on Power Debug E40 from Lauterbach.