Optimizing techniques for neural network architectures aimed at the edge are complex and intricate, which makes them non-universal. Edge computing and artificial intelligence overlap to enhance data security by enabling data processing at the source, mitigating any risk during data transfer. As data security concerns are growing among world governments, AI on edge has become a highly relevant field of modern research. There is a strict need to harness the power of Convolutional Neural Networks (CNNs) and Transformer networks on resource-constrained edge devices. Although many pruning and quantization techniques have been proposed for CNNs, they may not be directly applied to transformers due to the different computation patterns. This paper will explore the implications of two fundamental techniques: pruning and quantization. We will conduct a comparative analysis to explore the applicability of optimization techniques in Transformers, originally designed for CNNs, for real-world edge deployment. Experimental results show that significant improvement in compression ratio can be achieved while the accuracy of the transformer models is maintained.

Existing approximate Booth multipliers fail to keep up with modern approximate multipliers such as truncation-based approximate logarithmic multipliers. This paper introduces a new approximation scheme for Booth multipliers that can operate with negligible error rates using only$N/4$Booth decoders, instead of the traditional$N/2$Booth decoders. The proposed 16-bit BD16.4 approximate Booth multiplier reduces the Normalized Mean Error Deviation (NMED) by 96.5% and the Power-Area-Product (PAP) by 69.6%, when compared to a state-of-the-art approximate logarithmic multiplier. Additionally, the proposed BD16.4 approximate multiplier reduces the NMED by 94.4% and PAP by 74.8%, when compared to a state-of-the-art higher-radix approximate Booth multiplier. The proposed 8-bit approximate Booth multipliers reduce the NMED by up to 74% and PAP by up to 5% when compared to the existing state-of-the-art approximate logarithmic multipliers. We validated the results derived in this paper through a neural network inference experiment, where the proposed approximate multipliers showed a negligible drop in inference accuracy compared to the exact Booth multipliers and the state-of-the-art approximate logarithmic multipliers (ALM). The proposed approximate multipliers achieved a Power-Delay-Product reduction of 63% (vs. exact) and 21.22% (vs. ALM) in 16-bit experiments and a reduction of 67% (vs. exact) and 8.75% (vs. ALM) in 8-bit experiments.