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Aneesh Dixit

dblp:349/0269 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2024
0000-0002-9450-1329ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Security and privacy · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
2 papers
Hardware security and side channels · 100%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Reconfigurable computing and FPGAs · 59% Electronic design automation · 20% Integrated circuit design · 20%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels
intellectual property protection
1.022024
STATION: State Encoding-Based Attack-Resilient Sequential Obfuscation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
FuncTeller: How Well Does eFPGA Hide Functionality? · USENIX Security Symposium 2023
Hardware security and side channels › hardware obfuscation › logic obfuscation
logic locking
0.812024
STATION: State Encoding-Based Attack-Resilient Sequential Obfuscation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Reconfigurable computing and FPGAs › reconfigurable architecture
embedded FPGA
0.712023
FuncTeller: How Well Does eFPGA Hide Functionality? · USENIX Security Symposium 2023
Electronic design automation
hardware verification and test
0.212024
STATION: State Encoding-Based Attack-Resilient Sequential Obfuscation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Integrated circuit design › digital circuit design
sequential circuit design
0.212024
STATION: State Encoding-Based Attack-Resilient Sequential Obfuscation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Hardware security and side channels
integrated circuit security
0.212023
FuncTeller: How Well Does eFPGA Hide Functionality? · USENIX Security Symposium 2023

Methods — techniques the papers use, named apart from their topics

structural attack · 1.5input-output query attack · 1.5finite state machine encoding · 1.5
YearPublicationVenuePosition
2024 STATION: State Encoding-Based Attack-Resilient Sequential Obfuscation
abstract
The unauthorized duplication of design intellectual property (IP) and illegal overproduction of integrated circuits (ICs) are hardware security threats plaguing the security of the globalized IC supply chain. Researchers have developed various countermeasures such as logic locking, layout camouflaging, and split manufacturing to overcome the security threat of IP piracy and unauthorized overproduction. Logic locking is a holistic solution among all countermeasures since it safeguards the design IP against untrusted entities, such as untrusted foundries, test facilities, or end-users throughout the globalized IC supply chain. There are well-known logic locking techniques for combinational circuits with well-established security properties; however, their sequential counterparts remain vulnerable. Since most practical designs are inherently sequential, it is essential to develop secure obfuscation techniques to protect sequential designs. This paper proposes a sequential obfuscation technique, STATION, building on the principles of finite state machine encoding schemes. STATION is resilient against various attacks on sequential obfuscation–input-output (I/O) query attacks and structural attacks, including the ones targeting sequential obfuscation–which have broken all state-of-the-art sequential obfuscation techniques. STATION achieves good resilience and desired security against various I/O and structural attacks, which we ascertain by launching 9 different attacks on all tested circuits. Moreover, STATION ensures tolerable overheads in power, performance, and area, such as 8.75%, 1.22%, and 5.63% on the largest tested circuit, containing 102 inputs, 7 outputs, 6.1×104 gates, 7 flip flops, 100 states, and 3.0×103 transitions.
Zhaokun Han, Aneesh Dixit, Satwik Patnaik, Jeyavijayan Rajendran
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2023 FuncTeller: How Well Does eFPGA Hide Functionality?
Zhaokun Han, Mohammed Shayan, Aneesh Dixit, Mustafa M. Shihab, Yiorgos Makris, Jeyavijayan Rajendran
USENIX Security Symposium3