This paper addresses the speed bottleneck issue of traditional column-parallel analog-to-digital conversion circuits during the readout process of ultra-large array CMOS image sensors. A high-speed and low-power ADC based on a pipelined/time-to-digital converter hybrid architecture is proposed. This method is based on TDC technology to reduce the parasitic capacitance at the output of the MDAC circuit without compromising the conversion rate of the pipelined architecture, thus achieving a significant reduction in system power consumption. Additionally, the circuit multiplexing technology further enhances the power efficiency of the system. The proposed ADC method has been implemented and verified in a CMOS image sensor chip with an array size of 8192(H)$\times 8192$(V), manufactured with the 55 nm 1P4M CMOS process. Operating at the conditions of a clock frequency of 10 MHz and an input signal range of 1.6 V, the 13-bit ADC achieves a conversion rate of 5 MSPS, an SNDR of 73.82 dB, and an ENOB of 11.97 bits with a power consumption of$214.9~\mu $W. Compared with advanced ADCs, the proposed ADC achieves an optimal FOM1value of 0.011 pJ/step, effectively addressing the design contradiction between power consumption and conversion rate in traditional architectures. This chip achieves a row time of 200 ns and a frame rate of 610 fps with 5.23 W of power consumption.