Bit-serial RISC-V cores cover a distinctive corner in the design space, making them particularly interesting for highly area-constrained, ultra-low-cost applications in the IoT and extreme edge computing, such as smart sensors or single-use healthcare devices. Given their stringent focus on area demand, each feature must be carefully considered. One is the use of RISC-V compressed instructions by the RVC extension to reduce the memory footprint and, consequently, costs. While compressed instructions reduce the required ROM size by 22.4% on average in the Embench suite, the RVC extension is costly in terms of hardware resources. This work proposes three RVC implementations for the bit-serial FazyRV core and provides an in-depth analysis of their implications. We utilize open-source tools wherever applicable and base our evaluations on the iCE40, ECP5, GateMate, and 7-Series FPGA architectures, as well as estimates for an IHP-SG13G2 ASIC implementation. Our findings highlight the hardware cost of supporting compressed instructions in bit-serial cores, which increases the implementation size by 14.5% to 58% in a 1-bit FazyRV variant. Ultimately, none of the proposed RVC implementations is optimal for all targets. Thus, we provide guidance on decisions to be made in conjunction with the target architecture, the intended system performance, and the firmware.

Custom hardware instructions are frequently used to accelerate software. However, the number of active custom instructions - and speedup opportunities - are limited in resourceconstrained systems, such as those using small embedded FPGAs (eFPGAs). Hence, it is desirable to be able to dynamically reconfigure this resource to allow an application to change the accelerator logic. While an existing method called CX Table is described the Draft CX Specification to manage accelerators, it is not suitable for lightweight embedded systems because (1) virtual memory is required to isolate processes, and (2) an implied table lookup is required when switching custom instruction sets. This paper presents CIA Direct, a lightweight alternative to CX Table. It moves the table into a privileged control register to avoid virtual memory and external memory accesses. It provides inter-process virtualization of accelerator state, but intra-process virtualization has performance limitations. This paper also describes CxBex, the first ASIC implementation of CIA Direct. It contains a hard RISC-V processor with an eFPGA to support multiple custom instruction accelerators under dynamic reconfiguration. Unique to CxBex, context switching keeps multiple independent state context intact in eFPGA block during reconfiguration. Intended for lightweight embedded systems, this work demonstrates that the CIA Direct approach is simpler, reduces CPU complexity, eliminates dependence on external memory, and manages dynamic reconfiguration using exceptions.

RISC-V processor cores with a 32-bit internal data path reach a boundary on their minimal size, requiring novel concepts to decrease silicon area and the cost of Internet of Things (IoT) devices. We propose a minimal-area open-source RV32I RISC-V core targeting the IoT and low-workload applications. Unlike cores with a similarly small area, FazyRV is inherently scalable to a data path width of 1, 2, 4, or 8 bits. FazyRV has manifold variants to achieve the smallest footprint at given performance requirements. This paper provides insight into FazyRV, its verification, and the resource utilization for five Field-Programmable Gate Array (FPGA) architectures. We also compare its performance with similar cores using the Embench benchmark suite. Based on the findings, we analyze and discuss optimization potentials in depth. Although FazyRV is implemented at the register transfer level, we achieve comparable results to hand-optimized cores at the gate level. In an exemplary IoT application, the whole system on chip is implemented in 77 Slices, or 645 Logic Cells for a Xilinx/AMD 7-Series or an iCE40 FPGA, respectively.

Rising digital design complexity and demands for a shorter time to market increasingly challenge functional correctness. Formal verification can prevent flaws due to ambiguities and hard-to-find corner case issues. However, it is primarily attributed to verification engineers and formal experts. We consider that (a) Formal Property Verification (FPV) for sanity checking can contribute to finding flaws early, and (b) more guidance can promote a higher adoption rate by designers. Thus, we propose a concise, tool-agnostic, and flow-chart-based methodology to demystify FPV from a designer's perspective. We showcase the flow in two case studies using designs with different formal suitability, walk through the parts & phases to make the steps more tangible, and point out the limitations.