The increasing demand for high-performance computing in modern applications has intensified the need for energy efficient digital design at GHz frequencies. While adiabatic logics offer the potential for energy efficient operation, frequency range of energy saving for these logics is fundamentally bound to lower frequencies. However, in practice adiabatic logics lose their energy efficiency before reaching this fundamental frequency and their energy efficiency at higher frequency is practically limited by circuit level non-idealities such as race condition and short circuit conduction. Thus, in this paper, by structurally minimizing non-adiabatic energy dissipation caused by race condition and short circuit conduction, an energy efficient high performance adiabatic logic (HPAL) family is proposed. HPAL employs a novel dual amplitude power clocking scheme and non-interfering charge and discharge path to reduce the energy dissipation. Post-layout simulation results of different gates show the superiority of HPAL in energy efficiency over its CMOS and adiabatic counterparts. Furthermore, the simulation results of multiplier benchmark, including 64 four-bit multipliers and 192 buffers operating at 1.31GHz, show that even by including the energy dissipation of sinusoidal clock generator, HPAL consumes at least 60% lower energy per cycle and 30% lower energy per operation, compared to CMOS counterpart. These results indicate that HPAL overcomes key limitations of conventional adiabatic logic at high frequencies and provides a practical path toward energy efficient digital systems for compute-intensive applications at GHz regime.

Due to the higher energy and hardware efficiency of spiking neural networks (SNNs) compared to deep neural networks, they have attracted a lot of attention. However, their security must be investigated, given that they have access to private and confidential data. Physically unclonable functions (PUFs) are a class of circuits with security applications like device authentication, embedded licensing, device-specific cryptographic key generation, and anti-counterfeiting. Therefore, PUFs can be used to enhance the security of SNN. Accordingly, in this paper, an MTJ-based LIF Neuron/PUF has been proposed. The proposed design can function as both a LIF neuron and PUF. The results of the Monte Carlo simulation show that the proposed design has better uniqueness and uniformity values compared to its counterparts. These values for the proposed design are $50.07 \%$ and $49.66 \%$, which are close to their ideal value of $50 \%$. Also, the mean value of Shannon entropy for the 128-bit PUF response of the proposed design is 0.9974, which is close to its ideal value of 1.

Modern applications such as the Internet of Things (IoT) devices, AI, and automotive applications widely use field-programmable gate arrays (FPGAs). However, many of these applications have limited power resources. Also, the existing FPGAs are vulnerable to side-channel attacks (SCAs) such as correlation-based power analysis (CPA) attacks. Therefore, designing low-power, CPA-resistant, and secure-by-design FPGA is required. In this article, two low-power and CPA-resistant hybrid CMOS/magnetic tunnel junction (MTJ) logic-in-memory-based configurable logic blocks (CLBs) have been proposed and compared to a state-of-the-art counterpart. The first proposed design is single output, and the second one is multioutput. The simulation results show that compared to the state-of-the-art secure CLB counterpart [secured CLB (sCLB) by Zooker et al. (2020)], the proposed CLB designs have 42% and 33% lower delay, 85% and 18% lower power consumption, and 86% and 63% fewer equivalent transistors. To implement one round of the PRESENT algorithm, the first and second designs have 85% and 77% fewer transistors, 42% and 33% lower delay, and 86% and 50% lower power consumption compared to their silicon-proven secure counterpart. Also, to implement convolution layers of binarized neural network (BNN), compared to this counterpart, the first and second proposed designs have 85% and 90% fewer equivalent transistors, 42% and 33% lower delay, and 86% and 79% lower power consumption. Also, the resiliency of the proposed designs against power analysis attacks has been investigated by exhaustive simulations and performing CPA attacks on PRESENT and Advanced Encryption Standard (AES) SBOX. Also, this resiliency has been investigated for different tunnel magnetoresistance ratios (TMRs) and supply voltages.