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Yingbing Huang

dblp:349/4530 · DBLP profile ↗
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7ranked-venue papers
1as first author
7since 2021 · last 2025
0009-0004-8244-2917ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 4 · 4 since 2021Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
4 papers
Reinforcement learning · 25% Efficient and distributed learning · 25% Learning theory · 22%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 56% Electronic design automation · 44%
Interdisciplinary, comprehensive, and emerging computing
1 paper
Computing education · 77% Computational science and engineering · 23%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 15 heaviest of 18, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Natural language and speech › Language models and text generation
large language model evaluation
0.912025
Toward Engineering AGI: Benchmarking the Engineering Design Capabilities of LLMs · NeurIPS 2025
Computing education › STEM education
engineering design education
0.912025
Toward Engineering AGI: Benchmarking the Engineering Design Capabilities of LLMs · NeurIPS 2025
Machine learning › Reinforcement learning › imitation learning › occupancy matching
adversarial imitation learning
0.812024
Adversarial Imitation Learning via Boosting · ICLR 2024
Machine learning › Reinforcement learning
imitation learning
0.812024
Adversarial Imitation Learning via Boosting · ICLR 2024
Machine learning › Efficient and distributed learning
inference efficiency
0.812024
SnapKV: LLM Knows What You are Looking for Before Generation · NeurIPS 2024
Machine learning › Efficient and distributed learning › KV cache management
KV cache compression
0.812024
SnapKV: LLM Knows What You are Looking for Before Generation · NeurIPS 2024
Compilers and program optimization
accelerator compilation
0.812024
Invited: New Solutions on LLM Acceleration, Optimization, and Application · DAC 2024
Electronic design automation
hardware/software co-design
0.812024
Invited: New Solutions on LLM Acceleration, Optimization, and Application · DAC 2024
Hardware accelerators and domain-specific architectures › machine learning accelerator › transformer accelerator
large language model accelerator
0.812024
Invited: New Solutions on LLM Acceleration, Optimization, and Application · DAC 2024
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.812024
Invited: New Solutions on LLM Acceleration, Optimization, and Application · DAC 2024
Machine learning › Learning theory › sample complexity
active learning sample complexity
0.712023
Active representation learning for general task space with applications in robotics · NeurIPS 2023
Machine learning › Learning paradigms › multi-task learning › multi-task transfer learning
multi-task pretraining
0.712023
Active representation learning for general task space with applications in robotics · NeurIPS 2023
Machine learning › Learning theory
sample complexity
0.712023
Active representation learning for general task space with applications in robotics · NeurIPS 2023
Electronic design automation
hardware verification and test
0.212024
Invited: New Solutions on LLM Acceleration, Optimization, and Application · DAC 2024
Electronic design automation › hardware verification and test › hardware verification
high-level synthesis verification
0.212024
Invited: New Solutions on LLM Acceleration, Optimization, and Application · DAC 2024

Methods — techniques the papers use, named apart from their topics

simulation-based evaluation · 1.7high-level synthesis · 1.5replay buffer · 0.8ensemble of policies · 0.8discriminator · 0.8boosting · 0.8attention head analysis · 0.8KV cache compression · 0.8nonlinear analysis · 0.7meta-algorithm · 0.7bilinear analysis · 0.7
YearPublicationVenuePosition
2025 Invited Paper: Hardware-Software Co-Design for Highly Optimized, Customized, and Reliable AI Systems
abstract
Over the past decade, AI has been rapidly integrated into our daily life, coming in every shape and size and working across systems from big clouds to IoT. As a result, AI systems are increasingly requiring enhancements in model efficiency, hardware acceleration, and memory systems to satisfy stringent constraints on efficiency, reliability, and security. However, advancing across these fronts is challenging as compute demand outpaces Moore’s-law efficiency, hardening into an AI compute wall and an AI energy wall. Breaking through requires a unified AI co-design loop that co-optimizes algorithms and hardware, including efficient AI-to-hardware mapping, so that ongoing goals (accuracy, sparsity, latency) align with concrete hardware choices (precision modes, interconnects, memory hierarchies) and AI-specific execution and memory-reuse patterns. This paper details the principal co-design challenges, presents complementary strategies, and outlines a practical roadmap toward highly optimized, efficient, reliable, and secure AI systems.
Jörg Henkel, Mehdi Baradaran Tahoori, Heba Khdr, Hassan Nassar, Vincent Meyers, Deming Chen, Selin Yildirim, Yingbing Huang, Nirmal Saxena, Saurabh Hukerikar, Srivi Dhruvanarayan
ICCAD8
2025 Toward Engineering AGI: Benchmarking the Engineering Design Capabilities of LLMs
abstract
Modern engineering, spanning electrical, mechanical, aerospace, civil, and computer disciplines, stands as a cornerstone of human civilization and the foundation of our society. However, engineering design poses a fundamentally different challenge for large language models (LLMs) compared with traditional textbook-style problem solving or factual question answering. Although existing benchmarks have driven progress in areas such as language understanding, code synthesis, and scientific problem solving, real-world engineering design demands the synthesis of domain knowledge, navigation of complex trade-offs, and management of the tedious processes that consume much of practicing engineers' time. Despite these shared challenges across engineering disciplines, no benchmark currently captures the unique demands of engineering design work. In this work, we introduce EngDesign, an Engineering Design benchmark that evaluates LLMs' abilities to perform practical design tasks across nine engineering domains. Unlike existing benchmarks that focus on factual recall or question answering, EngDesign uniquely emphasizes LLMs' ability to synthesize domain knowledge, reason under constraints, and generate functional, objective-oriented engineering designs. Each task in EngDesign represents a real-world engineering design problem, accompanied by a detailed task description specifying design goals, constraints, and performance requirements. EngDesign pioneers a simulation-based evaluation paradigm that moves beyond textbook knowledge to assess genuine engineering design capabilities and shifts evaluation from static answer checking to dynamic, simulation-driven functional verification, marking a crucial step toward realizing the vision of engineering Artificial General Intelligence (AGI).
Xingang Guo, Xiangyi Kong, Yilan Jiang, Xiayu Zhao, Zhihua Gong, Daixuan Li, Tianle Sang, Beixiao Zhu, Gregory Jun, Yingbing Huang, Yuqi Xue, Rahul Dev Kundu, Qi Jian Lim, Luke Alexander Granger, Mohamed Badr Younis, Darioush Keivan, Nippun Sabharwal, Shreyanka Sinha, Prakhar Agarwal, Kojo Vandyck, Hanlin Mai, Aditya Venkatesh, Ayush Barik, Jiankun Yang, Chongying Yue, Jingjie He, Licheng Xu, Liujun Xu, Rushabh Shetty, Ziheng Guo, Dahui Song, Manvi Jha, Weijie Liang, Weiman Yan, Bryan Zhang, Sahil Bhandary Karnoor, Rutva Pandya, Xinyi Gong, Mithesh Ballae Ganesh, Feize Shi, Ruiling Xu, Yanfeng Ouyang, Lianhui Qin, Elyse Rosenbaum, Corey Snyder, Peter J. Seiler, Geir E. Dullerud, Xiaojia Shelly Zhang, Zuofu Cheng, Pavan Kumar Hanumolu, Mayank Kulkarni, Mahdi Namazifar, Bin Hu 0002
NeurIPS12
2024 Invited Paper: Software/Hardware Co-design for LLM and Its Application for Design Verification
abstract
The widespread adoption of Large Language Models (LLMs) is impeded by their demanding compute and memory resources. The first task of this paper is to explore optimization strategies to expedite LLMs, including quantization, pruning, and operation-level optimizations. One unique direction is to optimize LLM inference through novel software/hardware co-design methods. Given the accelerated LLMs, the second task of this paper is to study LLMs’ performance in the usage scenario of circuit design and verification. Specifically, we place a particular emphasis on functional verification. Through automated prompt engineering, we harness the capabilities of the established LLM, GPT-4, to generate High-Level Synthesis (HLS) designs with predefined errors based on 11 open-source synthesizable HLS benchmark suites. This dataset is a comprehensive collection of over 1000 function-level designs, and each of which is afflicted with up to 45 distinct combinations of defects injected into the source code. This dataset, named Chrysalis, expands upon what’s available in current HLS error models, offering a rich resource for training to improve how LLMs debug code. The dataset can be accessed at: https://github.com/UIUC-ChenLab/Chrysalis-HLS.
Lily Jiaxin Wan, Yingbing Huang, Hanchen Ye, Xiaofan Zhang 0001, Deming Chen
ASPDAC2
2024 Invited: New Solutions on LLM Acceleration, Optimization, and Application
abstract
Large Language Models (LLMs) have revolutionized a wide range of applications with their strong human-like understanding and creativity. Due to the continuously growing model size and complexity, LLM training and deployment have shown significant challenges, which often results in extremely high computational and storage costs and energy consumption. In this paper, we discuss the recent advancements and research directions on (1) LLM algorithm-level acceleration, (2) LLM-hardware co-design for improved system efficiency, (3) LLM-to-accelerator compilation for customized LLM accelerators, and (4) LLM-aided design for HLS (High-Level Synthesis) functional verification. For each aspect, we present the background study, our proposed solutions, and future directions. An extended version of this work can be found at: https://arxiv.org/abs/2406.10903.
Yingbing Huang, Lily Jiaxin Wan, Hanchen Ye, Manvi Jha, Xiaofan Zhang 0001, Deming Chen
DAC1
2024 Adversarial Imitation Learning via Boosting
abstract
Adversarial imitation learning (AIL) has stood out as a dominant framework across various imitation learning (IL) applications, with Discriminator Actor Critic (DAC) demonstrating the effectiveness of off-policy learning algorithms in improving sample efficiency and scalability to higher-dimensional observations. Despite DAC’s empirical success, the original AIL objective is on-policy and DAC’s ad-hoc application of off-policy training does not guarantee successful imitation. Follow-up work such as ValueDICE tackles this issue by deriving a fully off-policy AIL objective. Instead in this work, we develop a novel and principled AIL algorithm via the framework of boosting. Like boosting, our new algorithm, AILBoost, maintains an ensemble of weighted weak learners (i.e., policies) and trains a discriminator that witnesses the maximum discrepancy between the distributions of the ensemble and the expert policy. We maintain a weighted replay buffer to represent the state-action distribution induced by the ensemble, allowing us to train discriminators using the entire data collected so far. Empirically, we evaluate our algorithm on both controller state-based and pixel-based environments from the DeepMind Control Suite. AILBoost outperforms DAC on both types of environments, demonstrating the benefit of properly weighting replay buffer data for off-policy training. On state-based environments, AILBoost outperforms ValueDICE and IQ-Learn, achieving state-of-the-art performance with as little as one expert trajectory.
Jonathan D. Chang, Dhruv Sreenivas, Yingbing Huang, Kianté Brantley, Wen Sun 0002
ICLR3
2024 SnapKV: LLM Knows What You are Looking for Before Generation
abstract
Large Language Models (LLMs) have made remarkable progress in processing extensive contexts, with the Key-Value (KV) cache playing a vital role in enhancing their performance. However, the growth of the KV cache in response to increasing input length poses challenges to memory and time efficiency. To address this problem, this paper introduces SnapKV, an innovative and fine-tuning-free approach that efficiently minimizes KV cache size while still delivering comparable performance in real-world applications. We discover that each attention head in the model consistently focuses on specific prompt attention features during generation. Meanwhile, this robust pattern can be obtained from an `observation' window located at the end of the prompts. Drawing on this insight, SnapKV automatically compresses KV caches by selecting clustered important KV positions for each attention head. Our approach significantly reduces the growing computational overhead and memory footprint when processing long input sequences. Specifically, SnapKV achieves a consistent decoding speed with a 3.6x increase in generation speed and an 8.2x enhancement in memory efficiency compared to baseline when processing inputs of 16K tokens. At the same time, it maintains comparable performance to baseline models across 16 long sequence datasets. Moreover, SnapKV can process up to 380K context tokens on a single A100-80GB GPU using HuggingFace implementation with minor changes, exhibiting only a negligible accuracy drop in the Needle-in-a-Haystack test. Further comprehensive studies suggest SnapKV's potential for practical applications.
Yingbing Huang, Bharat Venkitesh, Acyr Locatelli, Hanchen Ye, Tianle Cai, Patrick Lewis 0002, Deming Chen
NeurIPS2
2023 Active representation learning for general task space with applications in robotics
abstract
Representation learning based on multi-task pretraining has become a powerful approach in many domains. In particular, task-aware representation learning aims to learn an optimal representation for a specific target task by sampling data from a set of source tasks, while task-agnostic representation learning seeks to learn a universal representation for a class of tasks. In this paper, we propose a general and versatile algorithmic and theoretic framework for \emph{active representation learning}, where the learner optimally chooses which source tasks to sample from. This framework, along with a tractable meta algorithm, allows most arbitrary target and source task spaces (from discrete to continuous), covers both task-aware and task-agnostic settings, and is compatible with deep representation learning practices. We provide several instantiations under this framework, from bilinear and feature-based nonlinear to general nonlinear cases. In the bilinear case, by leveraging the non-uniform spectrum of the task representation and the calibrated source-target relevance, we prove that the sample complexity to achieve $\varepsilon$-excess risk on target scales with $(k^*)^2 ||v^*||_2^2 \varepsilon^{-2}$ where $k^*$ is the effective dimension of the target and $||v^*||_2^2 \in (0,1]$ represents the connection between source and target space. Compared to the passive one, this can save up to $\frac{1}{d_W}$ of sample complexity, where $d_W$ is the task space dimension. Finally, we demonstrate different instantiations of our meta algorithm in synthetic datasets and robotics problems, from pendulum simulations to real-world drone flight datasets. On average, our algorithms outperform baselines by 20%-70%.
Yifang Chen 0001, Yingbing Huang, Simon S. Du, Kevin Jamieson 0001, Guanya Shi
NeurIPS2