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Minggui Tang

dblp:349/5297 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2023
0009-0005-9814-0718ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 75% Electronic design automation · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs › coarse-grained reconfigurable architecture
CGRA mapping
0.712023
MapZero: Mapping for Coarse-grained Reconfigurable Architectures with Reinforcement Learning and Monte-Carlo Tree Search · ISCA 2023
Reconfigurable computing and FPGAs
coarse-grained reconfigurable architecture
0.712023
MapZero: Mapping for Coarse-grained Reconfigurable Architectures with Reinforcement Learning and Monte-Carlo Tree Search · ISCA 2023
Reconfigurable computing and FPGAs › application mapping
data flow graph mapping
0.712023
MapZero: Mapping for Coarse-grained Reconfigurable Architectures with Reinforcement Learning and Monte-Carlo Tree Search · ISCA 2023
Electronic design automation
high-level synthesis
0.712023
MapZero: Mapping for Coarse-grained Reconfigurable Architectures with Reinforcement Learning and Monte-Carlo Tree Search · ISCA 2023

Methods — techniques the papers use, named apart from their topics

reinforcement learning · 0.7monte carlo tree search · 0.7
YearPublicationVenuePosition
2023 MapZero: Mapping for Coarse-grained Reconfigurable Architectures with Reinforcement Learning and Monte-Carlo Tree Search
abstract
Coarse-grained reconfigurable architecture (CGRA) has become a promising candidate for data-intensive computing due to its flexibility and high energy efficiency. CGRA compilers map data flow graphs (DFGs) extracted from applications onto CGRAs, playing a fundamental role in fully exploiting hardware resources for acceleration. Yet the existing compilers are time-demanding and cannot guarantee optimal results due to the traversal search of enormous search spaces brought about by the spatio-temporal flexibility of CGRA structures and the complexity of DFGs. Inspired by the amazing progress in reinforcement learning (RL) and Monte-Carlo tree search (MCTS) for real-world problems, we consider constructing a compiler that can learn from past experiences and comprehensively understand the target DFG and CGRA.
Yi Huang 0036, Jianfeng Zhu 0001, Xingchen Man, Yang Liu 0326, Chunyang Feng, Pengfei Gou, Minggui Tang, Shaojun Wei, Leibo Liu
ISCA8